pinctrl: renesas: rzg2l: Add support for pull-up/down

Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.

Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.

Value | RZ/G2L        | RZ/V2H
---------------------------------
00b:  | Bias Disabled | Pull up/down disabled
01b:  | Pull-up       | Pull up/down disabled
10b:  | Pull-down     | Pull-down
11b:  | Prohibited    | Pull-up

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 0cebcb5fc7bedfb2f76101f47c4fae0f0bd0829a..d65823085bdaec2ae99bc948eadeef23c44cd6f1 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -129,6 +129,7 @@
 #define IOLH(off)              (0x1000 + (off) * 8)
 #define SR(off)                        (0x1400 + (off) * 8)
 #define IEN(off)               (0x1800 + (off) * 8)
+#define PUPD(off)              (0x1C00 + (off) * 8)
 #define ISEL(off)              (0x2C00 + (off) * 8)
 #define SD_CH(off, ch)         ((off) + (ch) * 4)
 #define ETH_POC(off, ch)       ((off) + (ch) * 4)
@@ -147,6 +148,7 @@
 #define IEN_MASK               0x01
 #define IOLH_MASK              0x03
 #define SR_MASK                        0x01
+#define PUPD_MASK              0x03
 
 #define PM_INPUT               0x1
 #define PM_OUTPUT              0x2
@@ -259,6 +261,8 @@ struct rzg2l_pinctrl_data {
        void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
        u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
        int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
+       int (*hw_to_bias_param)(unsigned int val);
+       int (*bias_param_to_hw)(enum pin_config_param param);
 };
 
 /**
@@ -1000,6 +1004,38 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
        return 0;
 }
 
+static int rzg2l_hw_to_bias_param(unsigned int bias)
+{
+       switch (bias) {
+       case 0:
+               return PIN_CONFIG_BIAS_DISABLE;
+       case 1:
+               return PIN_CONFIG_BIAS_PULL_UP;
+       case 2:
+               return PIN_CONFIG_BIAS_PULL_DOWN;
+       default:
+               break;
+       }
+
+       return -EINVAL;
+}
+
+static int rzg2l_bias_param_to_hw(enum pin_config_param param)
+{
+       switch (param) {
+       case PIN_CONFIG_BIAS_DISABLE:
+               return 0;
+       case PIN_CONFIG_BIAS_PULL_UP:
+               return 1;
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               return 2;
+       default:
+               break;
+       }
+
+       return -EINVAL;
+}
+
 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
                                     unsigned int _pin,
                                     unsigned long *config)
@@ -1058,6 +1094,23 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
                arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
                break;
 
+       case PIN_CONFIG_BIAS_DISABLE:
+       case PIN_CONFIG_BIAS_PULL_UP:
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               if (!(cfg & PIN_CFG_PUPD))
+                       return -EINVAL;
+
+               arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
+               ret = pctrl->data->hw_to_bias_param(arg);
+               if (ret < 0)
+                       return ret;
+
+               if (ret != param)
+                       return -EINVAL;
+               /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
+               arg = 1;
+               break;
+
        case PIN_CONFIG_DRIVE_STRENGTH: {
                unsigned int index;
 
@@ -1173,6 +1226,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
                        rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
                        break;
 
+               case PIN_CONFIG_BIAS_DISABLE:
+               case PIN_CONFIG_BIAS_PULL_UP:
+               case PIN_CONFIG_BIAS_PULL_DOWN:
+                       if (!(cfg & PIN_CFG_PUPD))
+                               return -EINVAL;
+
+                       ret = pctrl->data->bias_param_to_hw(param);
+                       if (ret < 0)
+                               return ret;
+
+                       rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);
+                       break;
+
                case PIN_CONFIG_DRIVE_STRENGTH:
                        arg = pinconf_to_config_argument(_configs[i]);
 
@@ -2645,6 +2711,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
        .pmc_writeb = &rzg2l_pmc_writeb,
        .oen_read = &rzg2l_read_oen,
        .oen_write = &rzg2l_write_oen,
+       .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+       .bias_param_to_hw = &rzg2l_bias_param_to_hw,
 };
 
 static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2660,6 +2728,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
        .pmc_writeb = &rzg2l_pmc_writeb,
        .oen_read = &rzg2l_read_oen,
        .oen_write = &rzg2l_write_oen,
+       .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+       .bias_param_to_hw = &rzg2l_bias_param_to_hw,
 };
 
 static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2674,6 +2744,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
        .pmc_writeb = &rzg2l_pmc_writeb,
        .oen_read = &rzg2l_read_oen,
        .oen_write = &rzg2l_write_oen,
+       .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+       .bias_param_to_hw = &rzg2l_bias_param_to_hw,
 };
 
 static const struct of_device_id rzg2l_pinctrl_of_table[] = {