+2013-05-16 Uros Bizjak <ubizjak@gmail.com>
+ Dzianis Kahanovich <mahatma@eu.by>
+
+ PR target/45359
+ PR target/46396
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect
+ VIA/Centaur processors and determine their cache parameters
+ using detect_caches_amd.
+
2013-05-16 Teresa Johnson <tejohnson@google.com>
* cfgrtl.c (verify_hot_cold_block_grouping): Return err.
2013-05-15 Uros Bizjak <ubizjak@gmail.com>
- * config/i386/i386.c (iy86_option_override_internal): Update
+ * config/i386/i386.c (ix86_option_override_internal): Update
processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add
PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry.
Do not enable SSE prefetch on non-SSE 3dNow! targets. Enable
if (!arch)
{
- if (vendor == signature_AMD_ebx)
+ if (vendor == signature_AMD_ebx
+ || vendor == signature_CENTAUR_ebx)
cache = detect_caches_amd (ext_level);
else if (vendor == signature_INTEL_ebx)
{
else
processor = PROCESSOR_PENTIUM;
}
+ else if (vendor == signature_CENTAUR_ebx)
+ {
+ if (arch)
+ {
+ if (family == 6)
+ {
+ if (model > 9)
+ /* Use the default detection procedure. */
+ processor = PROCESSOR_GENERIC32;
+ else if (model == 9)
+ cpu = "c3-2";
+ else if (model >= 6)
+ cpu = "c3";
+ else
+ /* We have no idea. */
+ processor = PROCESSOR_GENERIC32;
+ }
+ else if (has_3dnow)
+ cpu = "winchip2";
+ else if (has_mmx)
+ cpu = "winchip2-c6";
+ else
+ /* We have no idea. */
+ processor = PROCESSOR_GENERIC32;
+ }
+ }
else
{
switch (family)