+2020-07-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26305
+ * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
+ (%bp)/(%ebp)/(%rbp) for {disp32}.
+ * doc/c-i386.texi: Update {disp32} documentation.
+ * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
+ * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
+ * testsuite/gas/i386/pseudos.d: Updated.
+ * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
+
2020-07-27 H.J. Lu <hongjiu.lu@intel.com>
* doc/as.texi: Replace preceeded with preceded.
if (operand_type_check (i.types[op], disp) == 0)
{
/* fake (%bp) into 0(%bp) */
- i.types[op].bitfield.disp8 = 1;
+ if (i.disp_encoding == disp_encoding_32bit)
+ /* NB: Use disp16 since there is no disp32
+ in 16-bit mode. */
+ i.types[op].bitfield.disp16 = 1;
+ else
+ i.types[op].bitfield.disp8 = 1;
fake_zero_displacement = 1;
}
}
if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
{
fake_zero_displacement = 1;
- i.types[op].bitfield.disp8 = 1;
+ if (i.disp_encoding == disp_encoding_32bit)
+ i.types[op].bitfield.disp32 = 1;
+ else
+ i.types[op].bitfield.disp8 = 1;
}
i.sib.scale = i.log2_scale_factor;
if (i.index_reg == 0)
@samp{@{disp8@}} -- prefer 8-bit displacement.
@item
-@samp{@{disp32@}} -- prefer 32-bit displacement.
+@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement.
@item
@samp{@{load@}} -- prefer load-form instruction.
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
#pass
{disp8} movaps 128(%eax),%xmm2
{disp32} movaps 128(%eax),%xmm2
+ movb (%ebp),%al
+ {disp8} movb (%ebp),%al
+ {disp32} movb (%ebp),%al
+
+ movb (%bx),%al
+ {disp8} movb (%bx),%al
+ {disp32} movb (%bx),%al
+
+ movb (%bp),%al
+ {disp8} movb (%bp),%al
+ {disp32} movb (%bp),%al
+
.intel_syntax noprefix
{vex3} vmovaps xmm2,xmm7
{vex3} {load} vmovaps xmm2,xmm7
movaps xmm2,XMMWORD PTR [eax+128]
{disp8} movaps xmm2,XMMWORD PTR [eax+128]
{disp32} movaps xmm2,XMMWORD PTR [eax+128]
+
+ mov al, BYTE PTR [ebp]
+ {disp8} mov al, BYTE PTR [ebp]
+ {disp32} mov al, BYTE PTR [ebp]
+
+ mov al, BYTE PTR [bx]
+ {disp8} mov al, BYTE PTR [bx]
+ {disp32} mov al, BYTE PTR [bx]
+
+ mov al, BYTE PTR [bp]
+ {disp8} mov al, BYTE PTR [bp]
+ {disp32} mov al, BYTE PTR [bp]
+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
#pass
{rex} phaddw (%rcx),%mm0
{rex} phaddw (%r8),%mm0
+ movb (%rbp),%al
+ {disp8} movb (%rbp),%al
+ {disp32} movb (%rbp),%al
+
+ movb (%ebp),%al
+ {disp8} movb (%ebp),%al
+ {disp32} movb (%ebp),%al
+
.intel_syntax noprefix
{vex3} vmovaps xmm2,xmm7
{vex3} {load} vmovaps xmm2,xmm7
{rex} movaps xmm2,XMMWORD PTR [r8]
{rex} phaddw mm0,QWORD PTR [rcx]
{rex} phaddw mm0,QWORD PTR [r8]
+
+ mov al, BYTE PTR [rbp]
+ {disp8} mov al, BYTE PTR [rbp]
+ {disp32} mov al, BYTE PTR [rbp]
+
+ mov al, BYTE PTR [ebp]
+ {disp8} mov al, BYTE PTR [ebp]
+ {disp32} mov al, BYTE PTR [ebp]