loongson.md (<u>div<mode>3, [...]): New patterns.

gcc/
2008-11-13  Ruan Beihong  <ruanbeihong@gmail.com>

	* config/mips/loongson.md (<u>div<mode>3, <u>mod<mode>3): New patterns.
	* config/mips/loongson2ef.md (ls2_imult): Handle imul3nc.
	(ls2_idiv): Likewise idiv3.
	(ls2_prefetch): New reservation.
	* config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF.
	* config/mips/mips.md (type): Add imul3nc and idiv3.
	(length): Handle idiv3.
	(any_mod): New code_iterator.
	(u): Handle MOD and UMOD.
	(mul<mode>3): Generate mul<mode>3_mul3_ls2ef on Loongson targets.
	(prefetch): Handle TARGET_LOONGSON_2EF.

From-SVN: r141835

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7698bddd115388a196c754afa282b0102bd3cd0a..ece73ea4ca09042f8e682f517693dfac71b0c1e0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2008-11-13  Ruan Beihong  <ruanbeihong@gmail.com>
+
+       * config/mips/loongson.md (<u>div<mode>3, <u>mod<mode>3): New patterns.
+       * config/mips/loongson2ef.md (ls2_imult): Handle imul3nc.
+       (ls2_idiv): Likewise idiv3.
+       (ls2_prefetch): New reservation.
+       * config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF.
+       * config/mips/mips.md (type): Add imul3nc and idiv3.
+       (length): Handle idiv3.
+       (any_mod): New code_iterator.
+       (u): Handle MOD and UMOD.
+       (mul<mode>3): Generate mul<mode>3_mul3_ls2ef on Loongson targets.
+       (prefetch): Handle TARGET_LOONGSON_2EF.
+
 2008-11-13  Jakub Jelinek  <jakub@redhat.com>
 
        PR c++/27017

diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index 98b5113fbb56d89b7665736cb483655fd6cf2994..8cdb5f466e9cd63c451ddf1cb19a615ae06f0ca4 100644 (file)
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -473,3 +473,23 @@
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "punpckl<V_stretch_half_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
+
+;; Integer division and modulus.
+
+(define_insn "<u>div<mode>3"
+  [(set (match_operand:GPR 0 "register_operand" "=&d")
+       (any_div:GPR (match_operand:GPR 1 "register_operand" "d")
+                    (match_operand:GPR 2 "register_operand" "d")))]
+  "TARGET_LOONGSON_2EF"
+  { return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); }
+  [(set_attr "type" "idiv3")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "<u>mod<mode>3"
+  [(set (match_operand:GPR 0 "register_operand" "=&d")
+       (any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
+                    (match_operand:GPR 2 "register_operand" "d")))]
+  "TARGET_LOONGSON_2EF"
+  { return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); }
+  [(set_attr "type" "idiv3")
+   (set_attr "mode" "<MODE>")])

diff --git a/gcc/config/mips/loongson2ef.md b/gcc/config/mips/loongson2ef.md
index 8d29482210221130aa5bdb8cbe3fda8bcb39b851..df3de33f809f8efcdc2b87b73b9eff740c47ce97 100644 (file)
--- a/gcc/config/mips/loongson2ef.md
+++ b/gcc/config/mips/loongson2ef.md
@@ -160,14 +160,14 @@
 ;; Reservation for integer multiplication instructions.
 (define_insn_reservation "ls2_imult" 5
   (and (eq_attr "cpu" "loongson_2e,loongson_2f")
-       (eq_attr "type" "imul,imul3"))
+       (eq_attr "type" "imul,imul3nc"))
   "ls2_alu2,ls2_alu2_core")
 
 ;; Reservation for integer division / remainder instructions.
 ;; These instructions use the SRT algorithm and hence take 2-38 cycles.
 (define_insn_reservation "ls2_idiv" 20
   (and (eq_attr "cpu" "loongson_2e,loongson_2f")
-       (eq_attr "type" "idiv"))
+       (eq_attr "type" "idiv,idiv3"))
   "ls2_alu2,ls2_alu2_core*18")
 
 ;; Reservation for memory load instructions.
@@ -176,6 +176,11 @@
        (eq_attr "type" "load,fpload,mfc,mtc"))
   "ls2_mem")
 
+(define_insn_reservation "ls2_prefetch" 0
+  (and (eq_attr "cpu" "loongson_2e,loongson_2f")
+       (eq_attr "type" "prefetch,prefetchx"))
+  "ls2_mem")
+
 ;; Reservation for memory store instructions.
 ;; With stores we assume they don't alias with dependent loads.
 ;; Therefore we set the latency to zero.

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index bf2e0d0fae7b5c777804ceb7c6e23db2ef7e3a17..354c4c5f1c37d97a340802130e825d77b04e85c6 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -919,6 +919,7 @@ enum mips_code_readable_setting {
 
 /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
 #define ISA_HAS_PREFETCH       ((ISA_MIPS4                             \
+                                 || TARGET_LOONGSON_2EF                \
                                  || ISA_MIPS32                         \
                                  || ISA_MIPS32R2                       \
                                  || ISA_MIPS64                         \

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 3f56feb2ee9fc3ab1cbcb11475ea2284b8112697..222e41d7369acaffb3c4ef716effa6effa710e57 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -351,8 +351,10 @@
 ;; trap                trap if instructions
 ;; imul                integer multiply 2 operands
 ;; imul3       integer multiply 3 operands
+;; imul3nc     integer multiply 3 operands without clobbering HI/LO
 ;; imadd       integer multiply-add
-;; idiv                integer divide
+;; idiv                integer divide 2 operands
+;; idiv3       integer divide 3 operands
 ;; move                integer register move ({,D}ADD{,U} with rt = 0)
 ;; fmove       floating point register move
 ;; fadd                floating point add/subtract
@@ -376,9 +378,9 @@
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
    prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
-   shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
-   fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
-   frsqrt2,multi,nop,ghost"
+   shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+   fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
+   frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
   (cond [(eq_attr "jal" "!unset") (const_string "call")
         (eq_attr "got" "load") (const_string "load")
 
@@ -553,7 +555,7 @@
                    (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
          (const_int 8)
 
-         (eq_attr "type" "idiv")
+         (eq_attr "type" "idiv,idiv3")
          (symbol_ref "mips_idiv_insns () * 4")
          ] (const_int 4)))
 
@@ -787,6 +789,10 @@
 ;; from the same template.
 (define_code_iterator any_div [div udiv])
 
+;; This code iterator allows unsigned and signed modulus to be generated
+;; from the same template.
+(define_code_iterator any_mod [mod umod])
+
 ;; This code iterator allows all native floating-point comparisons to be
 ;; generated from the same template.
 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
@@ -809,6 +815,7 @@
 ;; "u" when doing an unsigned operation.
 (define_code_attr u [(sign_extend "") (zero_extend "u")
                     (div "") (udiv "u")
+                    (mod "") (umod "u")
                     (gt "") (gtu "u")
                     (ge "") (geu "u")
                     (lt "") (ltu "u")
@@ -1357,7 +1364,10 @@
                  (match_operand:GPR 2 "register_operand")))]
   ""
 {
-  if (ISA_HAS_<D>MUL3)
+  if (TARGET_LOONGSON_2EF)
+    emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
+                                          operands[2]));
+  else if (ISA_HAS_<D>MUL3)
     emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
   else if (TARGET_FIX_R4000)
     emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
@@ -1367,6 +1377,15 @@
   DONE;
 })
 
+(define_insn "mul<mode>3_mul3_ls2ef"
+  [(set (match_operand:GPR 0 "register_operand" "=d")
+        (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+                  (match_operand:GPR 2 "register_operand" "d")))]
+  "TARGET_LOONGSON_2EF"
+  "<d>multu.g\t%0,%1,%2"
+  [(set_attr "type" "imul3nc")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "mul<mode>3_mul3"
   [(set (match_operand:GPR 0 "register_operand" "=d,l")
        (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
@@ -6128,6 +6147,9 @@
             (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
+  if (TARGET_LOONGSON_2EF)
+    /* Loongson 2[ef] use load to $0 to perform prefetching.  */
+    return "ld\t$0,%a0";
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";
 }