net: mdio: mux-meson-gxl: set reversed bit when using internal phy

This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.

Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.

The vendor SDK sets this bit along with the PHY_ID bits.

Ported from the Linux change at [1] from Da Xu merged in
commit [2].

[1] https://lore.kernel.org/all/20250425192009.1439508-1-da@libre.computer/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")

Suggested-by: Da Xue <da@libre.computer>
Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/drivers/net/mdio_mux_meson_gxl.c b/drivers/net/mdio_mux_meson_gxl.c
index 8ef3ae598b77fabf7b992900141d309708428b13..31898ed437e4857dd7027d311ab496be3e448d16 100644 (file)
--- a/drivers/net/mdio_mux_meson_gxl.c
+++ b/drivers/net/mdio_mux_meson_gxl.c
@@ -19,6 +19,7 @@
 #define  REG2_LEDACT           GENMASK(23, 22)
 #define  REG2_LEDLINK          GENMASK(25, 24)
 #define  REG2_DIV4SEL          BIT(27)
+#define  REG2_REVERSED         BIT(28)
 #define  REG2_ADCBYPASS                BIT(30)
 #define  REG2_CLKINSEL         BIT(31)
 #define ETH_REG3               0x4
@@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
         * The only constraint is that it must match the one in
         * drivers/net/phy/meson-gxl.c to properly match the PHY.
         */
-       writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
+       writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
               priv->regs + ETH_REG2);
 
        /* Enable the internal phy */