spi: sh-msiof: Correct RX FIFO size for R-Car Gen2

According to Renesas Technical Updates TN-RCS-S068A/E, the MSIOF receive
FIFOs on R-Car Gen2 SoCs have room for 128 words of 32 bits.

Note that this change has no actual impact on the behavior of the
driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty
limited to the minimum of the transmit and receive FIFO sizes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/fd11933f932df81d84f417a21e2179bd4fdcfdc1.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index ea9277ab87f66cd594dd6d7025a4e3ea091ea35d..8d18a26128d600f63100551f78bfd10ae41a0a26 100644 (file)
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1099,7 +1099,7 @@ static const struct sh_msiof_chipdata rcar_gen2_data = {
        .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
                              SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
        .tx_fifo_size = 64,
-       .rx_fifo_size = 64,
+       .rx_fifo_size = 128,
        .ctlr_flags = SPI_CONTROLLER_MUST_TX,
        .min_div_pow = 0,
 };