return 0;
}
+static int mchp_tc_count_cap_read(struct counter_device *counter,
+ struct counter_count *count, size_t idx, u64 *val)
+{
+ struct mchp_tc_data *const priv = counter_priv(counter);
+ u32 cnt;
+ int ret;
+
+ switch (idx) {
+ case COUNTER_MCHP_EXCAP_RA:
+ ret = regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), &cnt);
+ break;
+ case COUNTER_MCHP_EXCAP_RB:
+ ret = regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), &cnt);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ *val = cnt;
+
+ return 0;
+}
+
+static int mchp_tc_count_cap_write(struct counter_device *counter,
+ struct counter_count *count, size_t idx, u64 val)
+{
+ struct mchp_tc_data *const priv = counter_priv(counter);
+ int ret;
+
+ if (val > U32_MAX)
+ return -ERANGE;
+
+ switch (idx) {
+ case COUNTER_MCHP_EXCAP_RA:
+ ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), val);
+ break;
+ case COUNTER_MCHP_EXCAP_RB:
+ ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static DEFINE_COUNTER_ARRAY_CAPTURE(mchp_tc_cnt_cap_array, 2);
+
+static struct counter_comp mchp_tc_count_ext[] = {
+ COUNTER_COMP_ARRAY_CAPTURE(mchp_tc_count_cap_read, mchp_tc_count_cap_write,
+ mchp_tc_cnt_cap_array),
+};
+
static struct counter_count mchp_tc_counts[] = {
{
.id = 0,
.num_functions = ARRAY_SIZE(mchp_tc_count_functions),
.synapses = mchp_tc_count_synapses,
.num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
+ .ext = mchp_tc_count_ext,
+ .num_ext = ARRAY_SIZE(mchp_tc_count_ext),
},
};
* Count 0
* \__ Synapse 0 -- Signal 0 (Channel A, i.e. TIOA)
* \__ Synapse 1 -- Signal 1 (Channel B, i.e. TIOB)
+ * \__ Extension capture0 (RA register)
+ * \__ Extension capture1 (RB register)
*
* It also supports the following events:
*
* - RC compare triggered
*/
+/* Capture extensions */
+#define COUNTER_MCHP_EXCAP_RA 0
+#define COUNTER_MCHP_EXCAP_RB 1
+
/* Event channels */
#define COUNTER_MCHP_EVCHN_CV 0
#define COUNTER_MCHP_EVCHN_RA 0