x86: Add Intel ENCLV to assembler and disassembler

gas/

	* testsuite/gas/i386/se1.s: Add enclv.
	* testsuite/gas/i386/x86-64-se1.s: Likewise.
	* testsuite/gas/i386/se1.d: Updated.
	* testsuite/gas/i386/x86-64-se1.d: Likewise.

opcodes/

	* i386-dis.c (rm_table): Add enclv.
	* i386-opc.tbl: Add enclv.
	* i386-tbl.h: Regenerated.

(cherry picked from commit a4e78aa5fed5ba2cc343c76b78d062291a6fb659)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 682ccb0e1770bb68e11d5e3188d8391956e0598d..f9d3bceebec00498ce4c16785efcf0c68dd781ea 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * testsuite/gas/i386/se1.s: Add enclv.
+       * testsuite/gas/i386/x86-64-se1.s: Likewise.
+       * testsuite/gas/i386/se1.d: Updated.
+       * testsuite/gas/i386/x86-64-se1.d: Likewise.
+
 2018-09-18  Tamar Christina  <tamar.christina@arm.com>
 
        * config/tc-aarch64.c (output_operand_error_report): Apply filtering to

diff --git a/gas/testsuite/gas/i386/se1.d b/gas/testsuite/gas/i386/se1.d
index ff2685c781d3ba22cb3529e89dfbf4acbfda655f..d7800ab885195693fc6003eea3807e9d8bb90e2b 100644 (file)
--- a/gas/testsuite/gas/i386/se1.d
+++ b/gas/testsuite/gas/i386/se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [      ]*[a-f0-9]+:    0f 01 cf                encls  
 [      ]*[a-f0-9]+:    0f 01 d7                enclu  
+[      ]*[a-f0-9]+:    0f 01 c0                enclv  
 #pass

diff --git a/gas/testsuite/gas/i386/se1.s b/gas/testsuite/gas/i386/se1.s
index 1b57ac87fe7c320f85ab8a2a6defbaa5313f0b81..92d57952c022b27a0bd9891fdafd843496c34381 100644 (file)
--- a/gas/testsuite/gas/i386/se1.s
+++ b/gas/testsuite/gas/i386/se1.s
@@ -5,3 +5,4 @@ _start:
 
        encls
        enclu
+       enclv

diff --git a/gas/testsuite/gas/i386/x86-64-se1.d b/gas/testsuite/gas/i386/x86-64-se1.d
index 29494f00901167fd86729c91e3eea62977fc0507..a515219406a8b7c8225766cf2de604856c3d93ad 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-se1.d
+++ b/gas/testsuite/gas/i386/x86-64-se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [      ]*[a-f0-9]+:    0f 01 cf                encls  
 [      ]*[a-f0-9]+:    0f 01 d7                enclu  
+[      ]*[a-f0-9]+:    0f 01 c0                enclv  
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-se1.s b/gas/testsuite/gas/i386/x86-64-se1.s
index 1b57ac87fe7c320f85ab8a2a6defbaa5313f0b81..92d57952c022b27a0bd9891fdafd843496c34381 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-se1.s
+++ b/gas/testsuite/gas/i386/x86-64-se1.s
@@ -5,3 +5,4 @@ _start:
 
        encls
        enclu
+       enclv

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 25ddce1378e8ff800c607cfab5e7f489cc628246..caa8db269e01747e93fc9228723537261509f9f0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (rm_table): Add enclv.
+       * i386-opc.tbl: Add enclv.
+       * i386-tbl.h: Regenerated.
+
 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/23418

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 42d219cb119f809af2be4970d6f18f0378de4b25..78436879fb0f3dd443b3673234609e764028d60e 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -12321,7 +12321,7 @@ static const struct dis386 rm_table[][8] = {
   },
   {
     /* RM_0F01_REG_0 */
-    { Bad_Opcode },
+    { "enclv",         { Skip_MODRM }, 0 },
     { "vmcall",                { Skip_MODRM }, 0 },
     { "vmlaunch",      { Skip_MODRM }, 0 },
     { "vmresume",      { Skip_MODRM }, 0 },

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 84ade356666d41cafddabe2a205f4e74e5857999..99f4d6635aa25ff8af58647ce9c641a7222191a2 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4100,6 +4100,7 @@ xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No
 
 encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // SGX instructions end.
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c37eea6d7c09216c549939c893078ab7baeb086..42ac313ecadc1db444d1e39c7959244ee5866ca3 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -83658,6 +83658,20 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0 } } } },
+  { "enclv", 0, 0xf01c0, None, 3,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0 } } } },
   { "vcvtpd2udqx", 2, 0x79, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0,