/* disable IIR coeff SRAM access */
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
COEFF_SRAM_CTRL,
- (unsigned long)~COEFF_SRAM_CTRL);
+ ~COEFF_SRAM_CTRL);
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
CLR_IIR_HISTORY | IIR_EN | IIR_STAGE_MASK,
CLR_IIR_HISTORY | IIR_EN |
} else {
/* disable IIR */
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
- IIR_EN, (unsigned long)~IIR_EN);
+ IIR_EN, ~IIR_EN);
}
/* CON3 setting (RX OFS) */
ASM_ON, ASM_ON);
else
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
- ASM_ON, (unsigned long)~ASM_ON);
+ ASM_ON, ~ASM_ON);
return 0;
}