--- /dev/null
+From 58e7b1d5826ac6a64b1101d8a70162bc084a7d1e Mon Sep 17 00:00:00 2001
+From: Ludovic Desroches <ludovic.desroches@atmel.com>
+Date: Fri, 22 Nov 2013 17:08:43 +0100
+Subject: ARM: at91: sama5d3: reduce TWI internal clock frequency
+
+From: Ludovic Desroches <ludovic.desroches@atmel.com>
+
+commit 58e7b1d5826ac6a64b1101d8a70162bc084a7d1e upstream.
+
+With some devices, transfer hangs during I2C frame transmission. This issue
+disappears when reducing the internal frequency of the TWI IP. Even if it is
+indicated that internal clock max frequency is 66MHz, it seems we have
+oversampling on I2C signals making TWI believe that a transfer in progress
+is done.
+
+This fix has no impact on the I2C bus frequency.
+
+Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
+Acked-by: Wolfram Sang <wsa@the-dreams.de>
+Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-at91/sama5d3.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/mach-at91/sama5d3.c
++++ b/arch/arm/mach-at91/sama5d3.c
+@@ -95,19 +95,19 @@ static struct clk twi0_clk = {
+ .name = "twi0_clk",
+ .pid = SAMA5D3_ID_TWI0,
+ .type = CLK_TYPE_PERIPHERAL,
+- .div = AT91_PMC_PCR_DIV2,
++ .div = AT91_PMC_PCR_DIV8,
+ };
+ static struct clk twi1_clk = {
+ .name = "twi1_clk",
+ .pid = SAMA5D3_ID_TWI1,
+ .type = CLK_TYPE_PERIPHERAL,
+- .div = AT91_PMC_PCR_DIV2,
++ .div = AT91_PMC_PCR_DIV8,
+ };
+ static struct clk twi2_clk = {
+ .name = "twi2_clk",
+ .pid = SAMA5D3_ID_TWI2,
+ .type = CLK_TYPE_PERIPHERAL,
+- .div = AT91_PMC_PCR_DIV2,
++ .div = AT91_PMC_PCR_DIV8,
+ };
+ static struct clk mmc0_clk = {
+ .name = "mci0_clk",
--- /dev/null
+From d8aa712c30148ba26fd89a5dc14de95d4c375184 Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Thu, 28 Nov 2013 21:43:40 +0000
+Subject: ARM: fix booting low-vectors machines
+
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+
+commit d8aa712c30148ba26fd89a5dc14de95d4c375184 upstream.
+
+Commit f6f91b0d9fd9 (ARM: allow kuser helpers to be removed from the
+vector page) required two pages for the vectors code. Although the
+code setting up the initial page tables was updated, the code which
+allocates page tables for new processes wasn't, neither was the code
+which tears down the mappings. Fix this.
+
+Fixes: f6f91b0d9fd9 ("ARM: allow kuser helpers to be removed from the vector page")
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/pgtable.h | 2 +-
+ arch/arm/mm/mmap.c | 2 +-
+ arch/arm/mm/pgd.c | 3 ++-
+ 3 files changed, 4 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/include/asm/pgtable.h
++++ b/arch/arm/include/asm/pgtable.h
+@@ -58,7 +58,7 @@ extern void __pgd_error(const char *file
+ * mapping to be mapped at. This is particularly important for
+ * non-high vector CPUs.
+ */
+-#define FIRST_USER_ADDRESS PAGE_SIZE
++#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
+
+ /*
+ * Use TASK_SIZE as the ceiling argument for free_pgtables() and
+--- a/arch/arm/mm/mmap.c
++++ b/arch/arm/mm/mmap.c
+@@ -146,7 +146,7 @@ arch_get_unmapped_area_topdown(struct fi
+
+ info.flags = VM_UNMAPPED_AREA_TOPDOWN;
+ info.length = len;
+- info.low_limit = PAGE_SIZE;
++ info.low_limit = FIRST_USER_ADDRESS;
+ info.high_limit = mm->mmap_base;
+ info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+ info.align_offset = pgoff << PAGE_SHIFT;
+--- a/arch/arm/mm/pgd.c
++++ b/arch/arm/mm/pgd.c
+@@ -87,7 +87,8 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
+ init_pud = pud_offset(init_pgd, 0);
+ init_pmd = pmd_offset(init_pud, 0);
+ init_pte = pte_offset_map(init_pmd, 0);
+- set_pte_ext(new_pte, *init_pte, 0);
++ set_pte_ext(new_pte + 0, init_pte[0], 0);
++ set_pte_ext(new_pte + 1, init_pte[1], 0);
+ pte_unmap(init_pte);
+ pte_unmap(new_pte);
+ }
--- /dev/null
+From 67130c5464f50428aea0b4526a6729d61f9a1d53 Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Fri, 29 Nov 2013 00:54:38 +0000
+Subject: ARM: footbridge: fix EBSA285 LEDs
+
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+
+commit 67130c5464f50428aea0b4526a6729d61f9a1d53 upstream.
+
+- The LEDs register is write-only: it can't be read-modify-written.
+- The LEDs are write-1-for-off not 0.
+- The check for the platform was inverted.
+
+Fixes: cf6856d693dd ("ARM: mach-footbridge: retire custom LED code")
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-footbridge/ebsa285.c | 22 +++++++++++++---------
+ 1 file changed, 13 insertions(+), 9 deletions(-)
+
+--- a/arch/arm/mach-footbridge/ebsa285.c
++++ b/arch/arm/mach-footbridge/ebsa285.c
+@@ -30,21 +30,24 @@ static const struct {
+ const char *name;
+ const char *trigger;
+ } ebsa285_leds[] = {
+- { "ebsa285:amber", "heartbeat", },
+- { "ebsa285:green", "cpu0", },
++ { "ebsa285:amber", "cpu0", },
++ { "ebsa285:green", "heartbeat", },
+ { "ebsa285:red",},
+ };
+
++static unsigned char hw_led_state;
++
+ static void ebsa285_led_set(struct led_classdev *cdev,
+ enum led_brightness b)
+ {
+ struct ebsa285_led *led = container_of(cdev,
+ struct ebsa285_led, cdev);
+
+- if (b != LED_OFF)
+- *XBUS_LEDS |= led->mask;
++ if (b == LED_OFF)
++ hw_led_state |= led->mask;
+ else
+- *XBUS_LEDS &= ~led->mask;
++ hw_led_state &= ~led->mask;
++ *XBUS_LEDS = hw_led_state;
+ }
+
+ static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
+@@ -52,18 +55,19 @@ static enum led_brightness ebsa285_led_g
+ struct ebsa285_led *led = container_of(cdev,
+ struct ebsa285_led, cdev);
+
+- return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
++ return hw_led_state & led->mask ? LED_OFF : LED_FULL;
+ }
+
+ static int __init ebsa285_leds_init(void)
+ {
+ int i;
+
+- if (machine_is_ebsa285())
++ if (!machine_is_ebsa285())
+ return -ENODEV;
+
+- /* 3 LEDS All ON */
+- *XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
++ /* 3 LEDS all off */
++ hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
++ *XBUS_LEDS = hw_led_state;
+
+ for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
+ struct ebsa285_led *led;
--- /dev/null
+From 43659222e7a0113912ed02f6b2231550b3e471ac Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Thu, 28 Nov 2013 21:55:41 +0000
+Subject: ARM: footbridge: fix VGA initialisation
+
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+
+commit 43659222e7a0113912ed02f6b2231550b3e471ac upstream.
+
+It's no good setting vga_base after the VGA console has been
+initialised, because if we do that we get this:
+
+Unable to handle kernel paging request at virtual address 000b8000
+pgd = c0004000
+[000b8000] *pgd=07ffc831, *pte=00000000, *ppte=00000000
+0Internal error: Oops: 5017 [#1] ARM
+Modules linked in:
+CPU: 0 PID: 0 Comm: swapper Not tainted 3.12.0+ #49
+task: c03e2974 ti: c03d8000 task.ti: c03d8000
+PC is at vgacon_startup+0x258/0x39c
+LR is at request_resource+0x10/0x1c
+pc : [<c01725d0>] lr : [<c0022b50>] psr: 60000053
+sp : c03d9f68 ip : 000b8000 fp : c03d9f8c
+r10: 000055aa r9 : 4401a103 r8 : ffffaa55
+r7 : c03e357c r6 : c051b460 r5 : 000000ff r4 : 000c0000
+r3 : 000b8000 r2 : c03e0514 r1 : 00000000 r0 : c0304971
+Flags: nZCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel
+
+which is an access to the 0xb8000 without the PCI offset required to
+make it work.
+
+Fixes: cc22b4c18540 ("ARM: set vga memory base at run-time")
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-footbridge/common.c | 3 +++
+ arch/arm/mach-footbridge/dc21285.c | 2 --
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/mach-footbridge/common.c
++++ b/arch/arm/mach-footbridge/common.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/spinlock.h>
++#include <video/vga.h>
+
+ #include <asm/pgtable.h>
+ #include <asm/page.h>
+@@ -196,6 +197,8 @@ void __init footbridge_map_io(void)
+ iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+ pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
+ }
++
++ vga_base = PCIMEM_BASE;
+ }
+
+ void footbridge_restart(char mode, const char *cmd)
+--- a/arch/arm/mach-footbridge/dc21285.c
++++ b/arch/arm/mach-footbridge/dc21285.c
+@@ -18,7 +18,6 @@
+ #include <linux/irq.h>
+ #include <linux/io.h>
+ #include <linux/spinlock.h>
+-#include <video/vga.h>
+
+ #include <asm/irq.h>
+ #include <asm/mach/pci.h>
+@@ -291,7 +290,6 @@ void __init dc21285_preinit(void)
+ int cfn_mode;
+
+ pcibios_min_mem = 0x81000000;
+- vga_base = PCIMEM_BASE;
+
+ mem_size = (unsigned int)high_memory - PAGE_OFFSET;
+ for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
--- /dev/null
+From 96039f735e290281d0c8a08fc467de2cd610543d Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Mon, 25 Nov 2013 17:26:47 +0100
+Subject: ARM: mvebu: re-enable PCIe on Armada 370 DB
+
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+
+commit 96039f735e290281d0c8a08fc467de2cd610543d upstream.
+
+Commit 14fd8ed0a7fd19913 ("ARM: mvebu: Relocate Armada 370/XP PCIe
+device tree nodes") relocated the PCIe controller DT nodes one level
+up in the Device Tree, to reflect a more correct representation of the
+hardware introduced by the mvebu-mbus Device Tree binding.
+
+However, while most of the boards were properly adjusted accordingly,
+the Armada 370 DB board was left unchanged, and therefore, PCIe is
+seen as not enabled on this board. This patch fixes that by moving the
+PCIe controller node one level-up in armada-370-db.dts.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Fixes: 14fd8ed0a7fd19913 "ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes"
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/armada-370-db.dts | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-370-db.dts
++++ b/arch/arm/boot/dts/armada-370-db.dts
+@@ -95,22 +95,22 @@
+ spi-max-frequency = <50000000>;
+ };
+ };
++ };
+
+- pcie-controller {
++ pcie-controller {
++ status = "okay";
++ /*
++ * The two PCIe units are accessible through
++ * both standard PCIe slots and mini-PCIe
++ * slots on the board.
++ */
++ pcie@1,0 {
++ /* Port 0, Lane 0 */
++ status = "okay";
++ };
++ pcie@2,0 {
++ /* Port 1, Lane 0 */
+ status = "okay";
+- /*
+- * The two PCIe units are accessible through
+- * both standard PCIe slots and mini-PCIe
+- * slots on the board.
+- */
+- pcie@1,0 {
+- /* Port 0, Lane 0 */
+- status = "okay";
+- };
+- pcie@2,0 {
+- /* Port 1, Lane 0 */
+- status = "okay";
+- };
+ };
+ };
+ };
--- /dev/null
+From b6dda00cddcc71d2030668bc0cc0fed758c411c2 Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Date: Mon, 25 Nov 2013 17:26:46 +0100
+Subject: ARM: mvebu: use the virtual CPU registers to access coherency registers
+
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+
+commit b6dda00cddcc71d2030668bc0cc0fed758c411c2 upstream.
+
+The Armada XP provides a mechanism called "virtual CPU registers" or
+"per-CPU register banking", to access the per-CPU registers of the
+current CPU, without having to worry about finding on which CPU we're
+running. CPU0 has its registers at 0x21800, CPU1 at 0x21900, CPU2 at
+0x21A00 and CPU3 at 0x21B00. The virtual registers accessing the
+current CPU registers are at 0x21000.
+
+However, in the Device Tree node that provides the register addresses
+for the coherency unit (which is responsible for ensuring coherency
+between processors, and I/O coherency between processors and the
+DMA-capable devices), a mistake was made: the CPU0-specific registers
+were specified instead of the virtual CPU registers. This means that
+the coherency barrier needed for I/O coherency was not behaving
+properly when executed from a CPU different from CPU0. This patch
+fixes that by using the virtual CPU registers.
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Fixes: e60304f8cb7bb5 "arm: mvebu: Add hardware I/O Coherency support"
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/armada-370-xp.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/armada-370-xp.dtsi
++++ b/arch/arm/boot/dts/armada-370-xp.dtsi
+@@ -51,7 +51,7 @@
+
+ coherency-fabric@20200 {
+ compatible = "marvell,coherency-fabric";
+- reg = <0x20200 0xb0>, <0x21810 0x1c>;
++ reg = <0x20200 0xb0>, <0x21010 0x1c>;
+ };
+
+ serial@12000 {
crypto-scatterwalk-set-the-chain-pointer-indication-bit.patch
crypto-ccm-fix-handling-of-zero-plaintext-when-computing-mac.patch
crypto-authenc-find-proper-iv-address-in-ablkcipher-callback.patch
+arm-fix-booting-low-vectors-machines.patch
+arm-footbridge-fix-vga-initialisation.patch
+arm-footbridge-fix-ebsa285-leds.patch
+arm-at91-sama5d3-reduce-twi-internal-clock-frequency.patch
+arm-mvebu-use-the-virtual-cpu-registers-to-access-coherency-registers.patch
+arm-mvebu-re-enable-pcie-on-armada-370-db.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
