]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amd: Add helper to get partition config modes
authorLijo Lazar <lijo.lazar@amd.com>
Tue, 17 Sep 2024 08:24:11 +0000 (16:24 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 26 Sep 2024 21:06:18 +0000 (17:06 -0400)
Add helper to get supported/available partition config modes

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

index 83e54697f0ee83faf89395600978cdd28af4e1be..2d3fdb6c3161788b3a83e57bcbdde296510eaf0b 100644 (file)
@@ -1363,35 +1363,35 @@ static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
        return count;
 }
 
+static const char *xcp_desc[] = {
+       [AMDGPU_SPX_PARTITION_MODE] = "SPX",
+       [AMDGPU_DPX_PARTITION_MODE] = "DPX",
+       [AMDGPU_TPX_PARTITION_MODE] = "TPX",
+       [AMDGPU_QPX_PARTITION_MODE] = "QPX",
+       [AMDGPU_CPX_PARTITION_MODE] = "CPX",
+};
+
 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
                                                struct device_attribute *addr,
                                                char *buf)
 {
        struct drm_device *ddev = dev_get_drvdata(dev);
        struct amdgpu_device *adev = drm_to_adev(ddev);
-       char *supported_partition;
+       struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr;
+       int size = 0, mode;
+       char *sep = "";
 
-       /* TBD */
-       switch (NUM_XCC(adev->gfx.xcc_mask)) {
-       case 8:
-               supported_partition = "SPX, DPX, QPX, CPX";
-               break;
-       case 6:
-               supported_partition = "SPX, TPX, CPX";
-               break;
-       case 4:
-               supported_partition = "SPX, DPX, CPX";
-               break;
-       /* this seems only existing in emulation phase */
-       case 2:
-               supported_partition = "SPX, CPX";
-               break;
-       default:
-               supported_partition = "Not supported";
-               break;
+       if (!xcp_mgr || !xcp_mgr->avail_xcp_modes)
+               return sysfs_emit(buf, "Not supported\n");
+
+       for_each_inst(mode, xcp_mgr->avail_xcp_modes) {
+               size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]);
+               sep = ", ";
        }
 
-       return sysfs_emit(buf, "%s\n", supported_partition);
+       size += sysfs_emit_at(buf, size, "\n");
+
+       return size;
 }
 
 static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
index 32775260556f44324e56f10040b30ebf6461c878..2c54c05f2c16badecface8c8939028e79018f3d8 100644 (file)
@@ -97,6 +97,8 @@ struct amdgpu_xcp_mgr {
 
         /* Used to determine KFD memory size limits per XCP */
        unsigned int num_xcp_per_mem_partition;
+       uint32_t supp_xcp_modes;
+       uint32_t avail_xcp_modes;
 };
 
 struct amdgpu_xcp_mgr_funcs {
index 5e8833e4fed2a28fc4d9f3fed8e871d75baa6d33..2255ddbb51ceed1285a2a0793597bc91fe1500c1 100644 (file)
@@ -530,6 +530,57 @@ static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr,
        return ret;
 }
 
+static void
+__aqua_vanjaram_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)
+{
+       struct amdgpu_device *adev = xcp_mgr->adev;
+
+       xcp_mgr->supp_xcp_modes = 0;
+
+       switch (NUM_XCC(adev->gfx.xcc_mask)) {
+       case 8:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_QPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 6:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_TPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 4:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_DPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       /* this seems only existing in emulation phase */
+       case 2:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+       case 1:
+               xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
+                                         BIT(AMDGPU_CPX_PARTITION_MODE);
+               break;
+
+       default:
+               break;
+       }
+}
+
+static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)
+{
+       int mode;
+
+       xcp_mgr->avail_xcp_modes = 0;
+
+       for_each_inst(mode, xcp_mgr->supp_xcp_modes) {
+               if (__aqua_vanjaram_is_valid_mode(xcp_mgr, mode))
+                       xcp_mgr->avail_xcp_modes |= BIT(mode);
+       }
+}
+
 static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
                                               int mode, int *num_xcps)
 {
@@ -578,6 +629,8 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
        amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);
 
        ret = __aqua_vanjaram_post_partition_switch(xcp_mgr, flags);
+       if (!ret)
+               __aqua_vanjaram_update_available_partition_mode(xcp_mgr);
 unlock:
        if (flags & AMDGPU_XCP_OPS_KFD)
                amdgpu_amdkfd_unlock_kfd(adev);
@@ -673,6 +726,7 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
        if (ret)
                return ret;
 
+       __aqua_vanjaram_update_supported_modes(adev->xcp_mgr);
        /* TODO: Default memory node affinity init */
 
        return ret;