--- /dev/null
+From 6b96d705f3cf435b0b8835b12c9742513c77fed6 Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Mon, 19 Jan 2015 16:16:15 -0800
+Subject: drm/i915: BDW Fix Halo PCI IDs marked as ULT.
+
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+
+commit 6b96d705f3cf435b0b8835b12c9742513c77fed6 upstream.
+
+BDW with PCI-IDs ended in "2" aren't ULT, but HALO.
+Let's fix it and at least allow VGA to work on this units.
+
+v2: forgot ammend and v1 doesn't compile
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87220
+Cc: Xion Zhang <xiong.y.zhang@intel.com>
+Cc: Guo Jinxian <jinxianx.guo@intel.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2076,8 +2076,7 @@ struct drm_i915_cmd_table {
+ #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
+ (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
+ #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
+- ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
+- (INTEL_DEVID(dev) & 0xf) == 0x6 || \
++ ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
+ (INTEL_DEVID(dev) & 0xf) == 0xe))
+ #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
+ (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
--- /dev/null
+From 13f3fbe827d09e3182023c8c54058cbf97aa146e Mon Sep 17 00:00:00 2001
+From: Jeremiah Mahler <jmmahler@gmail.com>
+Date: Mon, 12 Jan 2015 11:01:03 -0800
+Subject: drm/i915: fix inconsistent brightness after resume
+
+From: Jeremiah Mahler <jmmahler@gmail.com>
+
+commit 13f3fbe827d09e3182023c8c54058cbf97aa146e upstream.
+
+commit 6dda730e55f412a6dfb181cae6784822ba463847
+Author: Jani Nikula <jani.nikula@intel.com>
+Date: Tue Jun 24 18:27:40 2014 +0300
+
+ drm/i915: respect the VBT minimum backlight brightness
+
+introduced a bug which resulted in inconsistent brightness levels on
+different machines. If a suspended was entered with the screen off some
+machines would resume with the screen at minimum brightness and others
+at maximum brightness.
+
+The following commands can be used to produce this behavior.
+
+ xset dpms force off
+ sleep 1
+ sudo systemctl suspend
+ (resume ...)
+
+The root cause of this problem is a comparison which checks to see if
+the backlight level is zero when the panel is enabled. If it is zero,
+it is set to the maximum level. Unfortunately, not all machines have a
+minimum level of zero. On those machines the level is left at the
+minimum instead of begin set to the maximum.
+
+Fix the bug by updating the comparison to check for the minimum
+backlight level instead of zero. Also, expand the comparison for
+the possible case when the level is less than the minimum.
+
+Fixes: 6dda730e55f4 ("respect the VBT minimum backlight brightness")
+Signed-off-by: Jeremiah Mahler <jmmahler@gmail.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_panel.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_panel.c
++++ b/drivers/gpu/drm/i915/intel_panel.c
+@@ -947,7 +947,7 @@ void intel_panel_enable_backlight(struct
+
+ WARN_ON(panel->backlight.max == 0);
+
+- if (panel->backlight.level == 0) {
++ if (panel->backlight.level <= panel->backlight.min) {
+ panel->backlight.level = panel->backlight.max;
+ if (panel->backlight.device)
+ panel->backlight.device->props.brightness =
--- /dev/null
+From f48a01651b1758550c4d3ee65ec726dfa0658780 Mon Sep 17 00:00:00 2001
+From: David Woodhouse <dwmw2@infradead.org>
+Date: Tue, 20 Jan 2015 17:21:42 +0000
+Subject: drm/i915: Init PPGTT before context enable
+
+From: David Woodhouse <dwmw2@infradead.org>
+
+commit f48a01651b1758550c4d3ee65ec726dfa0658780 upstream.
+
+Commit 82460d972 ("drm/i915: Rework ppgtt init to no require an aliasing
+ppgtt") introduced a regression on Broadwell, triggering the following
+IOMMU fault at startup:
+
+ vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
+ dmar: DRHD: handling fault status reg 2
+ dmar: DMAR:[DMA Write] Request device [00:02.0] fault addr 880000
+ DMAR:[fault reason 23] Unknown
+ fbcon: inteldrmfb (fb0) is primary device
+
+Further commentary from Daniel:
+
+I sugggested this change to David after staring at the offending patch
+for a while. I have no idea and theory whatsoever why this would upset
+the gpu less than the other way round. But it seems to work. David
+promised to chase hw people a bit more to get a more meaningful answer.
+
+Wrt the comment that this deletes: I've done some digging and afaict
+loading context before ppgtt enable was once required before our recent
+restructuring of the context/ppgtt init code: Before that context sw
+setup (i.e. allocating the default context) and hw setup was smashed
+together. Also the setup of the default context was the bit that
+actually allocated the aliasing ppgtt structures. Which is the reason
+for the context before ppgtt depency.
+
+Or was, since with all the untangling there's no no real depency any
+more (functional, who knows what the hw is doing), so the comment is
+just stale.
+
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gem.c | 19 ++++++-------------
+ 1 file changed, 6 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -4818,25 +4818,18 @@ i915_gem_init_hw(struct drm_device *dev)
+ for (i = 0; i < NUM_L3_SLICES(dev); i++)
+ i915_gem_l3_remap(&dev_priv->ring[RCS], i);
+
+- /*
+- * XXX: Contexts should only be initialized once. Doing a switch to the
+- * default context switch however is something we'd like to do after
+- * reset or thaw (the latter may not actually be necessary for HW, but
+- * goes with our code better). Context switching requires rings (for
+- * the do_switch), but before enabling PPGTT. So don't move this.
+- */
+- ret = i915_gem_context_enable(dev_priv);
++ ret = i915_ppgtt_init_hw(dev);
+ if (ret && ret != -EIO) {
+- DRM_ERROR("Context enable failed %d\n", ret);
++ DRM_ERROR("PPGTT enable failed %d\n", ret);
+ i915_gem_cleanup_ringbuffer(dev);
+-
+- return ret;
+ }
+
+- ret = i915_ppgtt_init_hw(dev);
++ ret = i915_gem_context_enable(dev_priv);
+ if (ret && ret != -EIO) {
+- DRM_ERROR("PPGTT enable failed %d\n", ret);
++ DRM_ERROR("Context enable failed %d\n", ret);
+ i915_gem_cleanup_ringbuffer(dev);
++
++ return ret;
+ }
+
+ return ret;
--- /dev/null
+From af1a7301c7cf8912dca03065d448c4437c5c239f Mon Sep 17 00:00:00 2001
+From: Bob Paauwe <bob.j.paauwe@intel.com>
+Date: Thu, 18 Dec 2014 09:51:26 -0800
+Subject: drm/i915: Only fence tiled region of object.
+
+From: Bob Paauwe <bob.j.paauwe@intel.com>
+
+commit af1a7301c7cf8912dca03065d448c4437c5c239f upstream.
+
+When creating a fence for a tiled object, only fence the area that
+makes up the actual tiles. The object may be larger than the tiled
+area and if we allow those extra addresses to be fenced, they'll
+get converted to addresses beyond where the object is mapped. This
+opens up the possiblity of writes beyond the end of object.
+
+To prevent this, we adjust the size of the fence to only encompass
+the area that makes up the actual tiles. The extra space is considered
+un-tiled and now behaves as if it was a linear object.
+
+Testcase: igt/gem_tiled_fence_overflow
+Reported-by: Dan Hettena <danh@ghs.com>
+Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gem.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -3050,6 +3050,13 @@ static void i965_write_fence_reg(struct
+ u32 size = i915_gem_obj_ggtt_size(obj);
+ uint64_t val;
+
++ /* Adjust fence size to match tiled area */
++ if (obj->tiling_mode != I915_TILING_NONE) {
++ uint32_t row_size = obj->stride *
++ (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
++ size = (size / row_size) * row_size;
++ }
++
+ val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
+ 0xfffff000) << 32;
+ val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
regulator-core-fix-race-condition-in-regulator_put.patch
drivers-net-cpsw-discard-dual-emac-default-vlan-configuration.patch
drm-fix-fb-helper-vs-mst-dangling-connector-ptrs-v2.patch
+drm-i915-only-fence-tiled-region-of-object.patch
+drm-i915-bdw-fix-halo-pci-ids-marked-as-ult.patch
+drm-i915-init-ppgtt-before-context-enable.patch
+drm-i915-fix-inconsistent-brightness-after-resume.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
