drm/i915/dsi: Enforce pipeline flush with DSI HS transfer

With all of the boundary conditions when streaming the commands B2B in our
validation (part of the reason we added the flush),  the Flush effectively
serializes the transmission of each command enqueued within the command
dispatcher to one per V. Blank line which simplifies the behavior of the
High Speed Arbitration.

So, unless we absolutely have to burst these to the Sink, we should be
using the Pipeline Flush bit to serialize the commands.

Bspec: 19742, 50193
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14247
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gareth Yu <gareth.yu@intel.com>
Link: https://lore.kernel.org/r/20250509092539.763389-1-gareth.yu@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ca7033251e916b48e6926edd708483c93b915d8f..28dab9320aedd466bfc57438b1acc8592cddfe24 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -192,12 +192,12 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
        else
                tmp &= ~PAYLOAD_PRESENT;
 
-       tmp &= ~VBLANK_FENCE;
+       tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH);
 
        if (enable_lpdt)
                tmp |= LP_DATA_TRANSFER;
        else
-               tmp &= ~LP_DATA_TRANSFER;
+               tmp |= PIPELINE_FLUSH;
 
        tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
        tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);

diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
index d4845ac65acce9b0af5384188aba003f445f6408..b601b7632339a54caa3e310fb9010708e605b1c7 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
@@ -272,6 +272,7 @@
 #define  PAYLOAD_PRESENT               (1 << 31)
 #define  LP_DATA_TRANSFER              (1 << 30)
 #define  VBLANK_FENCE                  (1 << 29)
+#define  PIPELINE_FLUSH                        (1 << 28)
 #define  PARAM_WC_MASK                 (0xffff << 8)
 #define  PARAM_WC_LOWER_SHIFT          8
 #define  PARAM_WC_UPPER_SHIFT          16