iommu/amd: Introduce generic function to set multibit feature value

Define generic function `iommu_feature_set()` to set the values
in the feature control register and replace `iommu_set_inv_tlb_timeout()`
with it.

Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Link: https://lore.kernel.org/r/20250307095822.2274-2-sarunkod@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 3f57bdd0a6598cac15b77eed52143ee1b8c53d9d..fe0672676551e0e43d497b6b622206676840e83c 100644 (file)
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -181,7 +181,7 @@
 #define CONTROL_IRTCACHEDIS    59
 #define CONTROL_SNPAVIC_EN     61
 
-#define CTRL_INV_TO_MASK       (7 << CONTROL_INV_TIMEOUT)
+#define CTRL_INV_TO_MASK       7
 #define CTRL_INV_TO_NONE       0
 #define CTRL_INV_TO_1MS                1
 #define CTRL_INV_TO_10MS       2

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 94aaa4b2a9031d9e4b14b6f04aa9004bfa11a411..2428d5c6c729b56f9914feee8fd0010eeec03b46 100644 (file)
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -411,33 +411,26 @@ static void iommu_set_device_table(struct amd_iommu *iommu)
                        &entry, sizeof(entry));
 }
 
-/* Generic functions to enable/disable certain features of the IOMMU. */
-void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
+static void iommu_feature_set(struct amd_iommu *iommu, u64 val, u64 mask, u8 shift)
 {
        u64 ctrl;
 
        ctrl = readq(iommu->mmio_base +  MMIO_CONTROL_OFFSET);
-       ctrl |= (1ULL << bit);
+       mask <<= shift;
+       ctrl &= ~mask;
+       ctrl |= (val << shift) & mask;
        writeq(ctrl, iommu->mmio_base +  MMIO_CONTROL_OFFSET);
 }
 
-static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
+/* Generic functions to enable/disable certain features of the IOMMU. */
+void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
 {
-       u64 ctrl;
-
-       ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
-       ctrl &= ~(1ULL << bit);
-       writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+       iommu_feature_set(iommu, 1ULL, 1ULL, bit);
 }
 
-static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
+static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 {
-       u64 ctrl;
-
-       ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
-       ctrl &= ~CTRL_INV_TO_MASK;
-       ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
-       writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+       iommu_feature_set(iommu, 0ULL, 1ULL, bit);
 }
 
 /* Function to enable the hardware */
@@ -2651,7 +2644,7 @@ static void iommu_init_flags(struct amd_iommu *iommu)
        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
 
        /* Set IOTLB invalidation timeout to 1s */
-       iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
+       iommu_feature_set(iommu, CTRL_INV_TO_1S, CTRL_INV_TO_MASK, CONTROL_INV_TIMEOUT);
 
        /* Enable Enhanced Peripheral Page Request Handling */
        if (check_feature(FEATURE_EPHSUP))