RISC-V: Support ssctr/smctr extensions with version 1.0.

https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0

The privileged spec v1.10 already removed the sfence.vm instruction, and the
encoding of sfence.vm instruction is overlapped with the sctrclr instruction
of ssctr/smctr.  But since the privileged spec v1.10 already removed the
sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we
had to remove the sfence.vm.

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr.
	(riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0.
	(riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr.
	(riscv_multi_subset_supports_ext): Likewise.
gas/
	* config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address):
	Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR.
	(riscv_is_priv_insn): Removed SFENCE_VM check.
	* testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no
	longer supported since privileged spec v1.10.
	* testsuite/gas/riscv/attribute-14.s: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr.s: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
	* testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr.
	* testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction.
	* testsuite/gas/riscv/smctr-ssctr.s: Likewise.
include/
	* opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed
	encoding macro for sfence.vm since encoding conflict.  Added CSR
	numbers for ssctr/smctr CSRs.
	* opcode/riscv.h (enum riscv_insn_class): Added
	INSN_CLASS_SMCTR_OR_SSCTR for sctrclr.
opcodes/
	* riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm
	since encoding conflict.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a609781bc04590aa124a3626068d4e7cd69ccf56..f354ba07f310dbcc23da109322632e81490dc841 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1259,6 +1259,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smaia", "+ssaia", check_implicit_always},
   {"smcsrind", "+sscsrind", check_implicit_always},
   {"smcntrpmf", "+zicsr", check_implicit_always},
+  {"smctr", "+zicsr", check_implicit_always},
   {"smstateen", "+ssstateen", check_implicit_always},
   {"smepmp", "+zicsr", check_implicit_always},
   {"smdbltrp", "+zicsr", check_implicit_always},
@@ -1267,6 +1268,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sscsrind", "+zicsr", check_implicit_always},
   {"sscofpmf", "+zicsr", check_implicit_always},
   {"sscounterenw", "+zicsr", check_implicit_always},
+  {"ssctr", "+zicsr", check_implicit_always},
   {"ssstateen", "+zicsr", check_implicit_always},
   {"sstc", "+zicsr", check_implicit_always},
   {"sstvala", "+zicsr", check_implicit_always},
@@ -1446,6 +1448,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smaia",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smcsrind",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smcntrpmf",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"smctr",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smepmp",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smrnmi",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
@@ -1455,6 +1458,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscsrind",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscofpmf",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscounterenw",     ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"ssctr",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sstc",             ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sstvala",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
@@ -2735,6 +2739,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zcmp");
     case INSN_CLASS_ZCMT:
       return riscv_subset_supports (rps, "zcmt");
+    case INSN_CLASS_SMCTR_OR_SSCTR:
+      return (riscv_subset_supports (rps, "smctr")
+             || riscv_subset_supports (rps, "ssctr"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -3025,6 +3032,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zcmp";
     case INSN_CLASS_ZCMT:
       return "zcmt";
+    case INSN_CLASS_SMCTR_OR_SSCTR:
+      return _("smctr' or `ssctr");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a915c8b4995bfa8eab47a42a1ed53b50585ba176..2fcde2158bbbdc9626ab87da6c17b1adb5253dac 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -82,6 +82,7 @@ enum riscv_csr_class
   CSR_CLASS_SMCSRIND,          /* Smcsrind */
   CSR_CLASS_SMCNTRPMF,         /* Smcntrpmf */
   CSR_CLASS_SMCNTRPMF_32,      /* Smcntrpmf, rv32 only */
+  CSR_CLASS_SMCTR,             /* Smctr */
   CSR_CLASS_SMRNMI,            /* Smrnmi */
   CSR_CLASS_SMSTATEEN,         /* Smstateen only */
   CSR_CLASS_SMSTATEEN_32,      /* Smstateen RV32 only */
@@ -102,6 +103,7 @@ enum riscv_csr_class
   CSR_CLASS_SSTC_AND_H,                /* Sstc only (with H) */
   CSR_CLASS_SSTC_32,           /* Sstc RV32 only */
   CSR_CLASS_SSTC_AND_H_32,     /* Sstc RV32 only (with H) */
+  CSR_CLASS_SSCTR,             /* Ssctr */
   CSR_CLASS_XTHEADVECTOR,      /* xtheadvector only */
 };
 
@@ -1105,6 +1107,7 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SMSTATEEN:
       extension = "smstateen";
       break;
+    case CSR_CLASS_SMCTR: extension = "smctr"; break;
     case CSR_CLASS_SSAIA:
     case CSR_CLASS_SSAIA_AND_H:
     case CSR_CLASS_SSAIA_32:
@@ -1150,6 +1153,7 @@ riscv_csr_address (const char *csr_name,
                      || csr_class == CSR_CLASS_SSTC_AND_H_32);
       extension = "sstc";
       break;
+    case CSR_CLASS_SSCTR: extension = "ssctr"; break;
     case CSR_CLASS_DEBUG:
       break;
     case CSR_CLASS_XTHEADVECTOR:
@@ -2800,10 +2804,7 @@ riscv_is_priv_insn (insn_t insn)
   return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
          || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
          || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
-         || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
-  /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
-     check it here to keep the compatible.  */
-         || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
+         || ((insn ^ MATCH_WFI) & MASK_WFI) == 0);
 }
 
 static symbolS *deferred_sym_rootP;

diff --git a/gas/testsuite/gas/riscv/attribute-14.s b/gas/testsuite/gas/riscv/attribute-14.s
index ddda6b996f838656d2a34dee989fd499794dca42..dcca2d8671d2116bee1ee12f2bc085a62770c362 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-14.s
+++ b/gas/testsuite/gas/riscv/attribute-14.s
@@ -12,8 +12,3 @@
 .ifdef priv_insn_d
        sfence.vma
 .endif
-
-       # Obselete priv instruction.
-.ifdef priv_insn_e
-       sfence.vm
-.endif

diff --git a/gas/testsuite/gas/riscv/attribute-14e.d b/gas/testsuite/gas/riscv/attribute-14e.d
deleted file mode 100644 (file)
index 47fdc2e..0000000
--- a/gas/testsuite/gas/riscv/attribute-14e.d
+++ /dev/null
@@ -1,8 +0,0 @@
-#as: -march-attr --defsym priv_insn_e=1
-#readelf: -A
-#source: attribute-14.s
-Attribute Section: riscv
-File Attributes
-  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index 2d85996ad5cc8d7d203e4aadabd4507360868c74..a1d1147188d29bd117072729acbae133333cee90 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -403,6 +403,11 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
   DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356
   DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420
+  DW_CFA_offset_extended_sf: r4430 \(sctrctl\) at cfa\+1336
+  DW_CFA_offset_extended_sf: r4431 \(sctrstatus\) at cfa\+1340
+  DW_CFA_offset_extended_sf: r4447 \(sctrdepth\) at cfa\+1404
+  DW_CFA_offset_extended_sf: r4686 \(vsctrctl\) at cfa\+2360
+  DW_CFA_offset_extended_sf: r4942 \(mctrctl\) at cfa\+3384
   DW_CFA_offset_extended: r4096 \(ustatus\) at cfa\+0
   DW_CFA_offset_extended_sf: r4100 \(uie\) at cfa\+16
   DW_CFA_offset_extended_sf: r4101 \(utvec\) at cfa\+20

diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index a4cf56dd7995c4cc3799d45b8657e41f41264e47..7b9d663cea2466de6160e9414aee5847cd71f05e 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -405,6 +405,12 @@ _start:
        .cfi_offset stimecmph, 1396
        .cfi_offset vstimecmp, 2356
        .cfi_offset vstimecmph, 2420
+       # Ssctr/Smctr extension
+       .cfi_offset sctrctl, 1336
+       .cfi_offset sctrstatus, 1340
+       .cfi_offset sctrdepth, 1404
+       .cfi_offset vsctrctl, 2360
+       .cfi_offset mctrctl, 3384
        # dropped
        .cfi_offset ustatus, 0
        .cfi_offset uie, 16

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index f36c7771e05127e6b4cab2c35fb0667ad23fea4a..75027b2fea4b194b2a1c5a5ea9750deb83b21969 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -831,6 +831,16 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+24d59073[     ]+csrw[         ]+vstimecmp,a1
 [      ]+[0-9a-f]+:[   ]+25d02573[     ]+csrr[         ]+a0,vstimecmph
 [      ]+[0-9a-f]+:[   ]+25d59073[     ]+csrw[         ]+vstimecmph,a1
+[      ]+[0-9a-f]+:[   ]+14e02573[     ]+csrr[         ]+a0,sctrctl
+[      ]+[0-9a-f]+:[   ]+14e59073[     ]+csrw[         ]+sctrctl,a1
+[      ]+[0-9a-f]+:[   ]+14f02573[     ]+csrr[         ]+a0,sctrstatus
+[      ]+[0-9a-f]+:[   ]+14f59073[     ]+csrw[         ]+sctrstatus,a1
+[      ]+[0-9a-f]+:[   ]+15f02573[     ]+csrr[         ]+a0,sctrdepth
+[      ]+[0-9a-f]+:[   ]+15f59073[     ]+csrw[         ]+sctrdepth,a1
+[      ]+[0-9a-f]+:[   ]+24e02573[     ]+csrr[         ]+a0,vsctrctl
+[      ]+[0-9a-f]+:[   ]+24e59073[     ]+csrw[         ]+vsctrctl,a1
+[      ]+[0-9a-f]+:[   ]+34e02573[     ]+csrr[         ]+a0,mctrctl
+[      ]+[0-9a-f]+:[   ]+34e59073[     ]+csrw[         ]+mctrctl,a1
 [      ]+[0-9a-f]+:[   ]+00002573[     ]+csrr[         ]+a0,ustatus
 [      ]+[0-9a-f]+:[   ]+00059073[     ]+csrw[         ]+ustatus,a1
 [      ]+[0-9a-f]+:[   ]+00402573[     ]+csrr[         ]+a0,uie

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 38feb097df0c07234ecddc3ff4817927487c8cc3..30c5600bb6e81bcacad847eacae3c2fea330cd55 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1639,6 +1639,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vstimecmph', needs `sstc' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
 .*Warning: invalid CSR `fflags', needs `f' extension
 .*Info: macro .*
 .*Warning: invalid CSR `fflags', needs `f' extension

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 603b17a34effb1c37c035e5b9069de34caa6ba46..9726721af2abf8ea3341f8aff6b9027acebe9fb2 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -831,6 +831,16 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+24d59073[     ]+csrw[         ]+vstimecmp,a1
 [      ]+[0-9a-f]+:[   ]+25d02573[     ]+csrr[         ]+a0,vstimecmph
 [      ]+[0-9a-f]+:[   ]+25d59073[     ]+csrw[         ]+vstimecmph,a1
+[      ]+[0-9a-f]+:[   ]+14e02573[     ]+csrr[         ]+a0,sctrctl
+[      ]+[0-9a-f]+:[   ]+14e59073[     ]+csrw[         ]+sctrctl,a1
+[      ]+[0-9a-f]+:[   ]+14f02573[     ]+csrr[         ]+a0,sctrstatus
+[      ]+[0-9a-f]+:[   ]+14f59073[     ]+csrw[         ]+sctrstatus,a1
+[      ]+[0-9a-f]+:[   ]+15f02573[     ]+csrr[         ]+a0,sctrdepth
+[      ]+[0-9a-f]+:[   ]+15f59073[     ]+csrw[         ]+sctrdepth,a1
+[      ]+[0-9a-f]+:[   ]+24e02573[     ]+csrr[         ]+a0,vsctrctl
+[      ]+[0-9a-f]+:[   ]+24e59073[     ]+csrw[         ]+vsctrctl,a1
+[      ]+[0-9a-f]+:[   ]+34e02573[     ]+csrr[         ]+a0,mctrctl
+[      ]+[0-9a-f]+:[   ]+34e59073[     ]+csrw[         ]+mctrctl,a1
 [      ]+[0-9a-f]+:[   ]+00002573[     ]+csrr[         ]+a0,ustatus
 [      ]+[0-9a-f]+:[   ]+00059073[     ]+csrw[         ]+ustatus,a1
 [      ]+[0-9a-f]+:[   ]+00402573[     ]+csrr[         ]+a0,uie

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 3b0f7825b7f7ef30edbbf007646ed6e02ba8781f..27efda18839c0f5e8599f1adec675c87b51cb50c 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1635,6 +1635,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vstimecmph', needs `sstc' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
 .*Warning: invalid CSR `fflags', needs `f' extension
 .*Info: macro .*
 .*Warning: invalid CSR `fflags', needs `f' extension

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 862359e1618230343589482b81052016a0677413..41b6b3e6cfedba371bde59406087f646ca37cc4e 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -831,6 +831,16 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+24d59073[     ]+csrw[         ]+vstimecmp,a1
 [      ]+[0-9a-f]+:[   ]+25d02573[     ]+csrr[         ]+a0,vstimecmph
 [      ]+[0-9a-f]+:[   ]+25d59073[     ]+csrw[         ]+vstimecmph,a1
+[      ]+[0-9a-f]+:[   ]+14e02573[     ]+csrr[         ]+a0,sctrctl
+[      ]+[0-9a-f]+:[   ]+14e59073[     ]+csrw[         ]+sctrctl,a1
+[      ]+[0-9a-f]+:[   ]+14f02573[     ]+csrr[         ]+a0,sctrstatus
+[      ]+[0-9a-f]+:[   ]+14f59073[     ]+csrw[         ]+sctrstatus,a1
+[      ]+[0-9a-f]+:[   ]+15f02573[     ]+csrr[         ]+a0,sctrdepth
+[      ]+[0-9a-f]+:[   ]+15f59073[     ]+csrw[         ]+sctrdepth,a1
+[      ]+[0-9a-f]+:[   ]+24e02573[     ]+csrr[         ]+a0,vsctrctl
+[      ]+[0-9a-f]+:[   ]+24e59073[     ]+csrw[         ]+vsctrctl,a1
+[      ]+[0-9a-f]+:[   ]+34e02573[     ]+csrr[         ]+a0,mctrctl
+[      ]+[0-9a-f]+:[   ]+34e59073[     ]+csrw[         ]+mctrctl,a1
 [      ]+[0-9a-f]+:[   ]+00002573[     ]+csrr[         ]+a0,0x0
 [      ]+[0-9a-f]+:[   ]+00059073[     ]+csrw[         ]+0x0,a1
 [      ]+[0-9a-f]+:[   ]+00402573[     ]+csrr[         ]+a0,0x4

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 88b27f39745566c4d77a7121eb2d0d0ee871fb8d..d9049c1e19b6d5b43a7e0bae6043f654612ae3c6 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1359,6 +1359,26 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vstimecmph', needs `sstc' extension
 .*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mctrctl', needs `smctr' extension
+.*Info: macro .*
 .*Warning: invalid CSR `ustatus' for the privileged spec `1.12'
 .*Info: macro .*
 .*Warning: invalid CSR `ustatus' for the privileged spec `1.12'

diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index d1c4cf6261de4e7bf4584047865f62b152dfc46a..fca072844603728f2678e1c49c41736340a458c5 100644 (file)
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -470,6 +470,13 @@
        csr vstimecmp
        csr vstimecmph
 
+       # Smctr/Ssctr
+       csr sctrctl
+       csr sctrstatus
+       csr sctrdepth
+       csr vsctrctl
+       csr mctrctl
+
        # Supported in previous priv spec, but dropped now
 
        csr ustatus             # 0x0   in 1.10, dropped in 1.12

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index fd1174059e5dd89b1c908f9e7704e6fd5a005ad1..981679bced01d1f021bb3614ed2dd54d5f3e2eae 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -114,6 +114,7 @@ All available -march extensions for RISC-V:
        smaia                                   1.0
        smcsrind                                1.0
        smcntrpmf                               1.0
+       smctr                                   1.0
        smepmp                                  1.0
        smrnmi                                  1.0
        smstateen                               1.0
@@ -123,6 +124,7 @@ All available -march extensions for RISC-V:
        sscsrind                                1.0
        sscofpmf                                1.0
        sscounterenw                            1.0
+       ssctr                                   1.0
        ssstateen                               1.0
        sstc                                    1.0
        sstvala                                 1.0

diff --git a/gas/testsuite/gas/riscv/smctr-ssctr.d b/gas/testsuite/gas/riscv/smctr-ssctr.d
new file mode 100644 (file)
index 0000000..ead1f23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smctr-ssctr.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_smctr_ssctr
+#source: smctr-ssctr.s
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+0:[   ]+10400073[     ]+sctrclr

diff --git a/gas/testsuite/gas/riscv/smctr-ssctr.s b/gas/testsuite/gas/riscv/smctr-ssctr.s
new file mode 100644 (file)
index 0000000..08cfab4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smctr-ssctr.s
@@ -0,0 +1 @@
+       sctrclr

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 166424226aa127d76c995e61a6ecc7fcbd086a5c..1696ac72e25e66582e9a65d4d3bbbed896bdc484 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -289,8 +289,6 @@
 #define MASK_MRET  0xffffffff
 #define MATCH_DRET 0x7b200073
 #define MASK_DRET  0xffffffff
-#define MATCH_SFENCE_VM 0x10400073
-#define MASK_SFENCE_VM  0xfff07fff
 #define MATCH_SFENCE_VMA 0x12000073
 #define MASK_SFENCE_VMA  0xfe007fff
 #define MATCH_WFI 0x10500073
@@ -2310,6 +2308,9 @@
 #define MASK_CM_JT 0xfc03
 #define MATCH_CM_JALT 0xa002
 #define MASK_CM_JALT 0xfc03
+/* Smctr/Ssctr instruction.  */
+#define MATCH_SCTRCLR 0x10400073
+#define MASK_SCTRCLR 0xffffffff
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -4196,6 +4197,12 @@
 #define CSR_STIMECMPH 0x15d
 #define CSR_VSTIMECMP 0x24d
 #define CSR_VSTIMECMPH 0x25d
+/* Smctr/Ssctr CSR addresses.  */
+#define CSR_SCTRCTL 0x14e
+#define CSR_SCTRSTATUS 0x14f
+#define CSR_SCTRDEPTH 0x15f
+#define CSR_VSCTRCTL 0x24e
+#define CSR_MCTRCTL 0x34e
 /* Unprivileged Floating-Point CSR addresses.  */
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
@@ -4362,7 +4369,6 @@ DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
-DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
@@ -4763,6 +4769,8 @@ DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
 /* Zcmt instructions.  */
 DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
 DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
+/* Smctr/Ssctr instruction.  */
+DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
@@ -5304,6 +5312,12 @@ DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_S
 DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Smctr/Ssctr CSRs.  */
+DECLARE_CSR(sctrctl, CSR_SCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Dropped CSRs.  */
 DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12)
 DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12)

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index de4c13fb6dbcbbce03c5edcc3b25263c6dc5715a..e7d2d7805ed439e7bab4af6fc775724c49888a27 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -522,6 +522,7 @@ enum riscv_insn_class
   INSN_CLASS_ZCMOP,
   INSN_CLASS_ZCMP,
   INSN_CLASS_ZCMT,
+  INSN_CLASS_SMCTR_OR_SSCTR,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 5680f6f96d6b4685cd645960e8b12d0aa06ed612..31f96abd82549a595f985a584c5dfe4503d38c03 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2244,13 +2244,14 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hret",       0, INSN_CLASS_I, "",    MATCH_HRET, MASK_HRET, match_opcode, 0 },
 {"mret",       0, INSN_CLASS_I, "",    MATCH_MRET, MASK_MRET, match_opcode, 0 },
 {"dret",       0, INSN_CLASS_I, "",    MATCH_DRET, MASK_DRET, match_opcode, 0 },
-{"sfence.vm",  0, INSN_CLASS_I, "",    MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
-{"sfence.vm",  0, INSN_CLASS_I, "s",   MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
 {"sfence.vma", 0, INSN_CLASS_I, "",    MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
 {"sfence.vma", 0, INSN_CLASS_I, "s",   MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS },
 {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
 {"wfi",        0, INSN_CLASS_I, "",    MATCH_WFI, MASK_WFI, match_opcode, 0 },
 
+/* Smctr/Ssctr instruction.  */
+{"sctrclr", 0, INSN_CLASS_SMCTR_OR_SSCTR, "", MATCH_SCTRCLR, MASK_SCTRCLR, match_opcode, 0 },
+
 /* Svinval instructions.  */
 {"sinval.vma",      0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
 {"sfence.w.inval",  0, INSN_CLASS_SVINVAL, "",    MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },