RISC-V: Add vector psabi checking.

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

There're two exceptions,
  - The vector_size attribute.
  - The intrinsic functions.

Some cases that need to add -Wno-psabi to ignore the warning.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
	warning flag if func is not builtin
	* config/riscv/riscv.cc
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_init_cumulative_args): The same as header.
	(riscv_get_arg_info): Add the checking.
	(riscv_function_value): Check the func return and set warning flag
	* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
	determine whether warning psabi or not.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/pr109244.C: Add the -Wno-psabi.
	* g++.target/riscv/rvv/base/pr109535.C: Same
	* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Same
	* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Same
	* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Same
	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Same
	* gcc.target/riscv/rvv/base/pr110109-2.c: Same
	* gcc.target/riscv/rvv/base/scalar_move-9.c: Same
	* gcc.target/riscv/rvv/base/spill-10.c: Same
	* gcc.target/riscv/rvv/base/spill-11.c: Same
	* gcc.target/riscv/rvv/base/spill-9.c: Same
	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Same
	* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Same
	* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Same
	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Same
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Same
	* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Same
	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.
	* gcc.target/riscv/vector-abi-6.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6db3a46c682629ec7335821e93f129ada16f399a..b23a9c124653c12ee61fd480c3d1f98b7607692e 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -303,4 +303,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
 #endif
 
 extern bool riscv_use_divmod_expander (void);
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
 #endif /* ! GCC_RISCV_PROTOS_H */

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index de30bf4e567b5e4906a72460cf636270f16b7dc3..dd5361c2bd2a6d8fb8517a38ab4bdecb0b76470e 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
                                   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+       break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+       if (TREE_CODE (f) == FIELD_DECL)
+         {
+           tree field_type = TREE_TYPE (f);
+           if (!TYPE_P (field_type))
+             break;
+
+           /* Ignore it if it's fixed length vector.  */
+           if (VECTOR_TYPE_P (field_type))
+             is_vector = riscv_scalable_vector_type_p (field_type);
+           else
+             is_vector = riscv_arg_has_vector (field_type);
+         }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+              "experimental stage and may changes in the upcoming version of "
+              "GCC.");
+      warned = 1;
+    }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+                           tree fntype ATTRIBUTE_UNUSED,
+                           rtx libname ATTRIBUTE_UNUSED,
+                           tree fndecl,
+                           int caller ATTRIBUTE_UNUSED)
+{
+  memset (cum, 0, sizeof (*cum));
+
+  if (fndecl)
+    {
+      const tree_function_decl &fn
+       = FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+      if (fn.built_in_class == NOT_BUILT_IN)
+         cum->rvv_psabi_warning = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
   info->gpr_offset = cum->num_gprs;
   info->fpr_offset = cum->num_fprs;
 
+  if (cum->rvv_psabi_warning)
+    {
+      /* Only check existing of vector type.  */
+      riscv_pass_in_vector_p (type);
+    }
+
   /* TODO: Currently, it will cause an ICE for --param
      riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
      let GCC generate loads/stores. Ideally, we should either warn the user not
@@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
     }
 
   memset (&args, 0, sizeof args);
-  return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+  const_tree arg_type = type;
+  if (func && DECL_RESULT (func))
+    {
+      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+      if (fn.built_in_class == NOT_BUILT_IN)
+       args.rvv_psabi_warning = 1;
+
+      arg_type = TREE_TYPE (DECL_RESULT (func));
+    }
+
+  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
 }
 
 /* Implement TARGET_PASS_BY_REFERENCE. */

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8aec2bbee34f0cbcebee0d41657b7a95..bfd9b7551bcdf79a19a49222b10a915ffb376928 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -677,6 +677,8 @@ typedef struct {
 
   /* Number of floating-point registers used so far, likewise.  */
   unsigned int num_fprs;
+
+  int rvv_psabi_warning;
 } CUMULATIVE_ARGS;
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -684,7 +686,8 @@ typedef struct {
    For a library call, FNTYPE is 0.  */
 
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
-  memset (&(CUM), 0, sizeof (CUM))
+  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
+                       (N_NAMED_ARGS) != -1)
 
 #define EPILOGUE_USES(REGNO)   riscv_epilogue_uses (REGNO)
 

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
index eebfc239d3a81a70bdb200699c6639da70e66382..b0ce04f49210ef5688db26da52fd9aaa5b18a740 100644 (file)
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */
 typedef int a;
 using c = float;
 template < typename > using e = int;

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
index 7013cfcf4ee5264ccbc5738722cf2a6658c48029..aec613f3f9708e7b5f73b4d6d0a35d2adbcb791d 100644 (file)
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */
 
 typedef long size_t;
 typedef signed char int8_t;

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index 809b185dd65c0f5fe1f3125a211e6c76e7805599..cc373465957235067d63004955647b87371591fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
 #include "riscv_vector.h"
 
 vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 1bca8467a16e4337143389a312a260b6ff99ac1b..2942e0b2e530ee8b44cbc8793d05dc4e9494dc28 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index 57d0241675ad6a848344799c40b55557adaf7e45..a6df1215c601ec644cd08c4dd27aad9ec0324fe5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 9563c8d27fa35805735f8cbf98c32b1b98259b8b..276173d02db99aac4be9a461927b01bd64cb682f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 #include "riscv_vector.h"
 
 vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index e8b5bf8c714107ac170880c3fdf19d8cb116dbb5..c1df69ace5782f3a9fea27b115098deadaba67b3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 80ee1b5f0c9382d7065db09925f44742ba6d301e..9c310bbf5900263c8e124ebda714b417c06773c9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d37857e24ab48fdfc03480df01345a527cea3fab..89c96c8ef5e811ac4333fccdb9ba96281b87b57a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index aa2e5e75330b597c8b4b7f95e4ecb491ed6bd237..179be1c8c5bcbeaceab470b48899d27f105d1667 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index ec673575b4b915a13bcd31ebcab683aa1efd55c0..5464a297670a11c034ad5c6240632d31295c3614 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 501d98c58975e23832cc9141c5493a8cc90d163f..51f4fac0a8bd185085a7bfadd5c68b625fb42802 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
 
 #include <riscv_vector.h>
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index fbcfb7b85011076028e69f9e89138b3bec1c0099..b27e5ccad09e5c415565e84d2a63e2658c85fc00 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index c951644de4be2d860f773d5558e8416dae75d11c..0e7c7cdbdd5ea205dbcc88917396c520c7c69423 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 1d82cc8de2ddf62e47a5a7a32a187e9288bf5e64..9ae79663adf591aa2234c0f80ce7e718b4d62bec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 1026b3f82f1482c7fb6caf5af5c20b87ab188e49..fc70c54c7fca21799371594eb1a88ccb539c2a39 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index b82e2490815fd625eeaca7f614d76a44b7169f12..0e76f676515103da349ec5160b93b6ebd3dacd6f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644 (file)
index 0000000..969f142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644 (file)
index 0000000..63d97d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644 (file)
index 0000000..90ece60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644 (file)
index 0000000..ecf6d4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644 (file)
index 0000000..6053e07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644 (file)
index 0000000..63bc4a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+    size_t n, int cond) {
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2();
+  for (size_t i = 0; i < n; i += 1)
+    {
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+      __riscv_vse32_v_i32m1(out, c, vl);
+    }
+}