tty: serial: fsl_lpuart: rename register variables more specifically

There are many fuzzy register variables in the lpuart driver, such as
temp, tmp, val, reg. Let's give these register variables more specific
names.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Link: https://lore.kernel.org/r/20250312023904.1343351-4-sherry.sun@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 3b48e320e7f4bb8e4e2aaf3e09b6784d0cfa4929..c8cc0a241fba49aa4713e75c32045c6689781112 100644 (file)
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -441,36 +441,36 @@ static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 
 static void lpuart_stop_tx(struct uart_port *port)
 {
-       u8 temp;
+       u8 cr2;
 
-       temp = readb(port->membase + UARTCR2);
-       temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
-       writeb(temp, port->membase + UARTCR2);
+       cr2 = readb(port->membase + UARTCR2);
+       cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+       writeb(cr2, port->membase + UARTCR2);
 }
 
 static void lpuart32_stop_tx(struct uart_port *port)
 {
-       u32 temp;
+       u32 ctrl;
 
-       temp = lpuart32_read(port, UARTCTRL);
-       temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
-       lpuart32_write(port, temp, UARTCTRL);
+       ctrl = lpuart32_read(port, UARTCTRL);
+       ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
+       lpuart32_write(port, ctrl, UARTCTRL);
 }
 
 static void lpuart_stop_rx(struct uart_port *port)
 {
-       u8 temp;
+       u8 cr2;
 
-       temp = readb(port->membase + UARTCR2);
-       writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
+       cr2 = readb(port->membase + UARTCR2);
+       writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2);
 }
 
 static void lpuart32_stop_rx(struct uart_port *port)
 {
-       u32 temp;
+       u32 ctrl;
 
-       temp = lpuart32_read(port, UARTCTRL);
-       lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
+       ctrl = lpuart32_read(port, UARTCTRL);
+       lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL);
 }
 
 static void lpuart_dma_tx(struct lpuart_port *sport)
@@ -599,7 +599,7 @@ static void lpuart_flush_buffer(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
        struct dma_chan *chan = sport->dma_tx_chan;
-       u32 val;
+       u32 fifo;
 
        if (sport->lpuart_dma_tx_use) {
                if (sport->dma_tx_in_progress) {
@@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *port)
        }
 
        if (lpuart_is_32(sport)) {
-               val = lpuart32_read(port, UARTFIFO);
-               val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
-               lpuart32_write(port, val, UARTFIFO);
+               fifo = lpuart32_read(port, UARTFIFO);
+               fifo |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
+               lpuart32_write(port, fifo, UARTFIFO);
        } else {
-               val = readb(port->membase + UARTCFIFO);
-               val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
-               writeb(val, port->membase + UARTCFIFO);
+               fifo = readb(port->membase + UARTCFIFO);
+               fifo |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
+               writeb(fifo, port->membase + UARTCFIFO);
        }
 }
 
@@ -642,7 +642,7 @@ static int lpuart_poll_init(struct uart_port *port)
        struct lpuart_port *sport = container_of(port,
                                        struct lpuart_port, port);
        unsigned long flags;
-       u8 temp;
+       u8 fifo;
 
        port->fifosize = 0;
 
@@ -650,9 +650,9 @@ static int lpuart_poll_init(struct uart_port *port)
        /* Disable Rx & Tx */
        writeb(0, port->membase + UARTCR2);
 
-       temp = readb(port->membase + UARTPFIFO);
+       fifo = readb(port->membase + UARTPFIFO);
        /* Enable Rx and Tx FIFO */
-       writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
+       writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
                        port->membase + UARTPFIFO);
 
        /* flush Tx and Rx FIFO */
@@ -694,7 +694,7 @@ static int lpuart32_poll_init(struct uart_port *port)
 {
        unsigned long flags;
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
-       u32 temp;
+       u32 fifo;
 
        port->fifosize = 0;
 
@@ -703,10 +703,10 @@ static int lpuart32_poll_init(struct uart_port *port)
        /* Disable Rx & Tx */
        lpuart32_write(port, 0, UARTCTRL);
 
-       temp = lpuart32_read(port, UARTFIFO);
+       fifo = lpuart32_read(port, UARTFIFO);
 
        /* Enable Rx and Tx FIFO */
-       lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
+       lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 
        /* flush Tx and Rx FIFO */
        lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
@@ -789,10 +789,10 @@ static void lpuart_start_tx(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port,
                        struct lpuart_port, port);
-       u8 temp;
+       u8 cr2;
 
-       temp = readb(port->membase + UARTCR2);
-       writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
+       cr2 = readb(port->membase + UARTCR2);
+       writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2);
 
        if (sport->lpuart_dma_tx_use) {
                if (!lpuart_stopped_or_empty(port))
@@ -806,14 +806,14 @@ static void lpuart_start_tx(struct uart_port *port)
 static void lpuart32_start_tx(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
-       u32 temp;
+       u32 ctrl;
 
        if (sport->lpuart_dma_tx_use) {
                if (!lpuart_stopped_or_empty(port))
                        lpuart_dma_tx(sport);
        } else {
-               temp = lpuart32_read(port, UARTCTRL);
-               lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
+               ctrl = lpuart32_read(port, UARTCTRL);
+               lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL);
 
                if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
                        lpuart32_transmit_buffer(sport);
@@ -1411,9 +1411,9 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
        dma_async_issue_pending(chan);
 
        if (lpuart_is_32(sport)) {
-               u32 temp = lpuart32_read(&sport->port, UARTBAUD);
+               u32 baud = lpuart32_read(&sport->port, UARTBAUD);
 
-               lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
+               lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD);
 
                if (sport->dma_idle_int) {
                        u32 ctrl = lpuart32_read(&sport->port, UARTCTRL);
@@ -1520,10 +1520,10 @@ static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termio
 static unsigned int lpuart_get_mctrl(struct uart_port *port)
 {
        unsigned int mctrl = 0;
-       u8 reg;
+       u8 cr1;
 
-       reg = readb(port->membase + UARTCR1);
-       if (reg & UARTCR1_LOOPS)
+       cr1 = readb(port->membase + UARTCR1);
+       if (cr1 & UARTCR1_LOOPS)
                mctrl |= TIOCM_LOOP;
 
        return mctrl;
@@ -1532,10 +1532,10 @@ static unsigned int lpuart_get_mctrl(struct uart_port *port)
 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 {
        unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
-       u32 reg;
+       u32 ctrl;
 
-       reg = lpuart32_read(port, UARTCTRL);
-       if (reg & UARTCTRL_LOOPS)
+       ctrl = lpuart32_read(port, UARTCTRL);
+       if (ctrl & UARTCTRL_LOOPS)
                mctrl |= TIOCM_LOOP;
 
        return mctrl;
@@ -1543,49 +1543,49 @@ static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 
 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-       u8 reg;
+       u8 cr1;
 
-       reg = readb(port->membase + UARTCR1);
+       cr1 = readb(port->membase + UARTCR1);
 
        /* for internal loopback we need LOOPS=1 and RSRC=0 */
-       reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
+       cr1 &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
        if (mctrl & TIOCM_LOOP)
-               reg |= UARTCR1_LOOPS;
+               cr1 |= UARTCR1_LOOPS;
 
-       writeb(reg, port->membase + UARTCR1);
+       writeb(cr1, port->membase + UARTCR1);
 }
 
 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-       u32 reg;
+       u32 ctrl;
 
-       reg = lpuart32_read(port, UARTCTRL);
+       ctrl = lpuart32_read(port, UARTCTRL);
 
        /* for internal loopback we need LOOPS=1 and RSRC=0 */
-       reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
+       ctrl &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
        if (mctrl & TIOCM_LOOP)
-               reg |= UARTCTRL_LOOPS;
+               ctrl |= UARTCTRL_LOOPS;
 
-       lpuart32_write(port, reg, UARTCTRL);
+       lpuart32_write(port, ctrl, UARTCTRL);
 }
 
 static void lpuart_break_ctl(struct uart_port *port, int break_state)
 {
-       u8 temp;
+       u8 cr2;
 
-       temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+       cr2 = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
 
        if (break_state != 0)
-               temp |= UARTCR2_SBK;
+               cr2 |= UARTCR2_SBK;
 
-       writeb(temp, port->membase + UARTCR2);
+       writeb(cr2, port->membase + UARTCR2);
 }
 
 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
 {
-       u32 temp;
+       u32 ctrl;
 
-       temp = lpuart32_read(port, UARTCTRL);
+       ctrl = lpuart32_read(port, UARTCTRL);
 
        /*
         * LPUART IP now has two known bugs, one is CTS has higher priority than the
@@ -1602,22 +1602,22 @@ static void lpuart32_break_ctl(struct uart_port *port, int break_state)
                 * Disable the transmitter to prevent any data from being sent out
                 * during break, then invert the TX line to send break.
                 */
-               temp &= ~UARTCTRL_TE;
-               lpuart32_write(port, temp, UARTCTRL);
-               temp |= UARTCTRL_TXINV;
-               lpuart32_write(port, temp, UARTCTRL);
+               ctrl &= ~UARTCTRL_TE;
+               lpuart32_write(port, ctrl, UARTCTRL);
+               ctrl |= UARTCTRL_TXINV;
+               lpuart32_write(port, ctrl, UARTCTRL);
        } else {
                /* Disable the TXINV to turn off break and re-enable transmitter. */
-               temp &= ~UARTCTRL_TXINV;
-               lpuart32_write(port, temp, UARTCTRL);
-               temp |= UARTCTRL_TE;
-               lpuart32_write(port, temp, UARTCTRL);
+               ctrl &= ~UARTCTRL_TXINV;
+               lpuart32_write(port, ctrl, UARTCTRL);
+               ctrl |= UARTCTRL_TE;
+               lpuart32_write(port, ctrl, UARTCTRL);
        }
 }
 
 static void lpuart_setup_watermark(struct lpuart_port *sport)
 {
-       u8 val, cr2, cr2_saved;
+       u8 fifo, cr2, cr2_saved;
 
        cr2 = readb(sport->port.membase + UARTCR2);
        cr2_saved = cr2;
@@ -1625,8 +1625,8 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
                        UARTCR2_RIE | UARTCR2_RE);
        writeb(cr2, sport->port.membase + UARTCR2);
 
-       val = readb(sport->port.membase + UARTPFIFO);
-       writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+       fifo = readb(sport->port.membase + UARTPFIFO);
+       writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
                        sport->port.membase + UARTPFIFO);
 
        /* flush Tx and Rx FIFO */
@@ -1696,14 +1696,14 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
 
 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
 {
-       u32 temp;
+       u32 ctrl;
 
        lpuart32_setup_watermark(sport);
 
-       temp = lpuart32_read(&sport->port, UARTCTRL);
-       temp |= UARTCTRL_RE | UARTCTRL_TE;
-       temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
-       lpuart32_write(&sport->port, temp, UARTCTRL);
+       ctrl = lpuart32_read(&sport->port, UARTCTRL);
+       ctrl |= UARTCTRL_RE | UARTCTRL_TE;
+       ctrl |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
+       lpuart32_write(&sport->port, ctrl, UARTCTRL);
 }
 
 static void rx_dma_timer_init(struct lpuart_port *sport)
@@ -1820,16 +1820,16 @@ static void lpuart_hw_setup(struct lpuart_port *sport)
 static int lpuart_startup(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
-       u8 temp;
+       u8 fifo;
 
        /* determine FIFO size and enable FIFO mode */
-       temp = readb(port->membase + UARTPFIFO);
+       fifo = readb(port->membase + UARTPFIFO);
 
-       sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
+       sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) &
                                            UARTPFIFO_FIFOSIZE_MASK);
        port->fifosize = sport->txfifo_size;
 
-       sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
+       sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) &
                                            UARTPFIFO_FIFOSIZE_MASK);
 
        lpuart_request_dma(sport);
@@ -1840,24 +1840,24 @@ static int lpuart_startup(struct uart_port *port)
 
 static void lpuart32_hw_disable(struct lpuart_port *sport)
 {
-       u32 temp;
+       u32 ctrl;
 
-       temp = lpuart32_read(&sport->port, UARTCTRL);
-       temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
+       ctrl = lpuart32_read(&sport->port, UARTCTRL);
+       ctrl &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
                  UARTCTRL_TIE | UARTCTRL_TE);
-       lpuart32_write(&sport->port, temp, UARTCTRL);
+       lpuart32_write(&sport->port, ctrl, UARTCTRL);
 }
 
 static void lpuart32_configure(struct lpuart_port *sport)
 {
-       u32 temp;
+       u32 ctrl;
 
-       temp = lpuart32_read(&sport->port, UARTCTRL);
+       ctrl = lpuart32_read(&sport->port, UARTCTRL);
        if (!sport->lpuart_dma_rx_use)
-               temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
+               ctrl |= UARTCTRL_RIE | UARTCTRL_ILIE;
        if (!sport->lpuart_dma_tx_use)
-               temp |= UARTCTRL_TIE;
-       lpuart32_write(&sport->port, temp, UARTCTRL);
+               ctrl |= UARTCTRL_TIE;
+       lpuart32_write(&sport->port, ctrl, UARTCTRL);
 }
 
 static void lpuart32_hw_setup(struct lpuart_port *sport)
@@ -1880,16 +1880,16 @@ static void lpuart32_hw_setup(struct lpuart_port *sport)
 static int lpuart32_startup(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
-       u32 temp;
+       u32 fifo;
 
        /* determine FIFO size */
-       temp = lpuart32_read(port, UARTFIFO);
+       fifo = lpuart32_read(port, UARTFIFO);
 
-       sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
+       sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) &
                                            UARTFIFO_FIFOSIZE_MASK);
        port->fifosize = sport->txfifo_size;
 
-       sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
+       sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) &
                                            UARTFIFO_FIFOSIZE_MASK);
 
        /*
@@ -1934,16 +1934,16 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport)
 static void lpuart_shutdown(struct uart_port *port)
 {
        struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
-       u8 temp;
+       u8 cr2;
        unsigned long flags;
 
        uart_port_lock_irqsave(port, &flags);
 
        /* disable Rx/Tx and interrupts */
-       temp = readb(port->membase + UARTCR2);
-       temp &= ~(UARTCR2_TE | UARTCR2_RE |
+       cr2 = readb(port->membase + UARTCR2);
+       cr2 &= ~(UARTCR2_TE | UARTCR2_RE |
                        UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
-       writeb(temp, port->membase + UARTCR2);
+       writeb(cr2, port->membase + UARTCR2);
 
        uart_port_unlock_irqrestore(port, flags);
 
@@ -2141,7 +2141,7 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
                                     unsigned int baudrate, bool use_rx_dma,
                                     bool use_tx_dma)
 {
-       u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
+       u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud;
        u32 clk = port->uartclk;
 
        /*
@@ -2170,9 +2170,9 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
                tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
 
                /* select best values between sbr and sbr+1 */
-               tmp = clk / (tmp_osr * (tmp_sbr + 1));
-               if (tmp_diff > (baudrate - tmp)) {
-                       tmp_diff = baudrate - tmp;
+               baud = clk / (tmp_osr * (tmp_sbr + 1));
+               if (tmp_diff > (baudrate - baud)) {
+                       tmp_diff = baudrate - baud;
                        tmp_sbr++;
                }
 
@@ -2194,23 +2194,23 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
                dev_warn(port->dev,
                         "unacceptable baud rate difference of more than 3%%\n");
 
-       tmp = lpuart32_read(port, UARTBAUD);
+       baud = lpuart32_read(port, UARTBAUD);
 
        if ((osr > 3) && (osr < 8))
-               tmp |= UARTBAUD_BOTHEDGE;
+               baud |= UARTBAUD_BOTHEDGE;
 
-       tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
-       tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
+       baud &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
+       baud |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
 
-       tmp &= ~UARTBAUD_SBR_MASK;
-       tmp |= sbr & UARTBAUD_SBR_MASK;
+       baud &= ~UARTBAUD_SBR_MASK;
+       baud |= sbr & UARTBAUD_SBR_MASK;
 
        if (!use_rx_dma)
-               tmp &= ~UARTBAUD_RDMAE;
+               baud &= ~UARTBAUD_RDMAE;
        if (!use_tx_dma)
-               tmp &= ~UARTBAUD_TDMAE;
+               baud &= ~UARTBAUD_TDMAE;
 
-       lpuart32_write(port, tmp, UARTBAUD);
+       lpuart32_write(port, baud, UARTBAUD);
 }
 
 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
@@ -3085,7 +3085,7 @@ static int lpuart_suspend_noirq(struct device *dev)
 static int lpuart_resume_noirq(struct device *dev)
 {
        struct lpuart_port *sport = dev_get_drvdata(dev);
-       u32 val;
+       u32 stat;
 
        pinctrl_pm_select_default_state(dev);
 
@@ -3094,8 +3094,8 @@ static int lpuart_resume_noirq(struct device *dev)
 
                /* clear the wakeup flags */
                if (lpuart_is_32(sport)) {
-                       val = lpuart32_read(&sport->port, UARTSTAT);
-                       lpuart32_write(&sport->port, val, UARTSTAT);
+                       stat = lpuart32_read(&sport->port, UARTSTAT);
+                       lpuart32_write(&sport->port, stat, UARTSTAT);
                }
        }