ARM: dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
-STM32MP131:
  -core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
  -storage: 3*SDMCC, 1*QSPI, FMC
  -com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
  -audio: 2*SAI
  -network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC

A second diversity layer exists for security features:
-STM32MP13xY, "Y" gives information:
 -Y = A/D means no cryp IP and no secure boot.
 -Y = C/F means cryp IP + secure boot.

This commit adds basic peripheral.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
new file mode 100644 (file)
index 0000000..86126dc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0>;
+               };
+       };
+
+       arm-pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>;
+               interrupt-parent = <&intc>;
+       };
+
+       clocks {
+               clk_axi: clk-axi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <266500000>;
+               };
+
+               clk_hse: clk-hse {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+
+               clk_hsi: clk-hsi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <64000000>;
+               };
+
+               clk_lsi: clk-lsi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <32000>;
+               };
+
+               clk_pclk3: clk-pclk3 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <104438965>;
+               };
+
+               clk_pclk4: clk-pclk4 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <133250000>;
+               };
+
+               clk_pll4_p: clk-pll4_p {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+
+               clk_pll4_r: clk-pll4_r {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <99000000>;
+               };
+       };
+
+       intc: interrupt-controller@a0021000 {
+               compatible = "arm,cortex-a7-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0xa0021000 0x1000>,
+                     <0xa0022000 0x2000>;
+       };
+
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupt-parent = <&intc>;
+               always-on;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&intc>;
+               ranges;
+
+               uart4: serial@40010000 {
+                       compatible = "st,stm32h7-uart";
+                       reg = <0x40010000 0x400>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_hsi>;
+                       status = "disabled";
+               };
+
+               syscfg: syscon@50020000 {
+                       compatible = "st,stm32mp157-syscfg", "syscon";
+                       reg = <0x50020000 0x400>;
+                       clocks = <&clk_pclk3>;
+               };
+
+               sdmmc1: mmc@58005000 {
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x00253180>;
+                       reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cmd_irq";
+                       clocks = <&clk_pll4_p>;
+                       clock-names = "apb_pclk";
+                       cap-sd-highspeed;
+                       cap-mmc-highspeed;
+                       max-frequency = <120000000>;
+                       status = "disabled";
+               };
+
+               iwdg2: watchdog@5a002000 {
+                       compatible = "st,stm32mp1-iwdg";
+                       reg = <0x5a002000 0x400>;
+                       clocks = <&clk_pclk4>, <&clk_lsi>;
+                       clock-names = "pclk", "lsi";
+                       status = "disabled";
+               };
+
+               bsec: efuse@5c005000 {
+                       compatible = "st,stm32mp15-bsec";
+                       reg = <0x5c005000 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       part_number_otp: part_number_otp@4 {
+                               reg = <0x4 0x2>;
+                       };
+                       ts_cal1: calib@5c {
+                               reg = <0x5c 0x2>;
+                       };
+                       ts_cal2: calib@5e {
+                               reg = <0x5e 0x2>;
+                       };
+               };
+
+               /*
+                * Break node order to solve dependency probe issue between
+                * pinctrl and exti.
+                */
+               pinctrl: pin-controller@50002000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "st,stm32mp135-pinctrl";
+                       ranges = <0 0x50002000 0x8400>;
+                       pins-are-numbered;
+
+                       gpioa: gpio@50002000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x0 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOA";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 0 16>;
+                       };
+
+                       gpiob: gpio@50003000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOB";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 16 16>;
+                       };
+
+                       gpioc: gpio@50004000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x2000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOC";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 32 16>;
+                       };
+
+                       gpiod: gpio@50005000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x3000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOD";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 48 16>;
+                       };
+
+                       gpioe: gpio@50006000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x4000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOE";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 64 16>;
+                       };
+
+                       gpiof: gpio@50007000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x5000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOF";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 80 16>;
+                       };
+
+                       gpiog: gpio@50008000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x6000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOG";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 96 16>;
+                       };
+
+                       gpioh: gpio@50009000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x7000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOH";
+                               ngpios = <15>;
+                               gpio-ranges = <&pinctrl 0 112 15>;
+                       };
+
+                       gpioi: gpio@5000a000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x8000 0x400>;
+                               clocks = <&clk_pclk4>;
+                               st,bank-name = "GPIOI";
+                               ngpios = <8>;
+                               gpio-ranges = <&pinctrl 0 128 8>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
new file mode 100644 (file)
index 0000000..0fb1386
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp131.dtsi"
+
+/ {
+       soc {
+               m_can1: can@4400e000 {
+                       compatible = "bosch,m_can";
+                       reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+                       reg-names = "m_can", "message_ram";
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "int0", "int1";
+                       clocks = <&clk_hse>, <&clk_pll4_r>;
+                       clock-names = "hclk", "cclk";
+                       bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+                       status = "disabled";
+               };
+
+               m_can2: can@4400f000 {
+                       compatible = "bosch,m_can";
+                       reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+                       reg-names = "m_can", "message_ram";
+                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "int0", "int1";
+                       clocks = <&clk_hse>, <&clk_pll4_r>;
+                       clock-names = "hclk", "cclk";
+                       bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/stm32mp135.dtsi b/arch/arm/boot/dts/stm32mp135.dtsi
new file mode 100644 (file)
index 0000000..abf2acd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp135.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp133.dtsi"
+
+/ {
+       soc {
+       };
+};

diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
new file mode 100644 (file)
index 0000000..fa6889e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+       soc {
+               cryp: crypto@54002000 {
+                       compatible = "st,stm32mp1-cryp";
+                       reg = <0x54002000 0x400>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_axi>;
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
new file mode 100644 (file)
index 0000000..fa6889e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+       soc {
+               cryp: crypto@54002000 {
+                       compatible = "st,stm32mp1-cryp";
+                       reg = <0x54002000 0x400>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_axi>;
+                       status = "disabled";
+               };
+       };
+};