arm64: dts: mediatek: mt8188: Add MIPI DSI nodes

Add two MIPI DSI nodes and the associated PHY nodes to support DSI
panels.
Individual board device tree should enable the nodes as needed.

Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20241014111053.2294519-4-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 5bb4a5d4e18188c866dcf677a28a64265824c1ef..8c15002498e0c22dfd2524385f4223c3fdde1e1c 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1844,6 +1844,26 @@
                        };
                };
 
+               mipi_tx_config0: dsi-phy@11c80000 {
+                       compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
+                       reg = <0 0x11c80000 0 0x1000>;
+                       clocks = <&clk26m>;
+                       clock-output-names = "mipi_tx0_pll";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               mipi_tx_config1: dsi-phy@11c90000 {
+                       compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
+                       reg = <0 0x11c90000 0 0x1000>;
+                       clocks = <&clk26m>;
+                       clock-output-names = "mipi_tx0_pll";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                i2c1: i2c@11e00000 {
                        compatible = "mediatek,mt8188-i2c";
                        reg = <0 0x11e00000 0 0x1000>,
@@ -2229,10 +2249,41 @@
                        mediatek,smi = <&vdo_smi_common>;
                };
 
+               disp_dsi0: dsi@1c008000 {
+                       compatible = "mediatek,mt8188-dsi";
+                       reg = <0 0x1c008000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DSI0>,
+                                <&vdosys0 CLK_VDO0_DSI0_DSI>,
+                                <&mipi_tx_config0>;
+                       clock-names = "engine", "digital", "hs";
+                       interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+                       phys = <&mipi_tx_config0>;
+                       phy-names = "dphy";
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       resets = <&vdosys0 MT8188_VDO0_RST_DSI0>;
+                       status = "disabled";
+               };
+
+               disp_dsi1: dsi@1c012000 {
+                       compatible = "mediatek,mt8188-dsi";
+                       reg = <0 0x1c012000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DSI1>,
+                                <&vdosys0 CLK_VDO0_DSI1_DSI>,
+                                <&mipi_tx_config1>;
+                       clock-names = "engine", "digital", "hs";
+                       interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
+                       phys = <&mipi_tx_config1>;
+                       phy-names = "dphy";
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       resets = <&vdosys0 MT8188_VDO0_RST_DSI1>;
+                       status = "disabled";
+               };
+
                vdosys0: syscon@1c01d000 {
                        compatible = "mediatek,mt8188-vdosys0", "syscon";
                        reg = <0 0x1c01d000 0 0x1000>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                        mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
                        mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
                };