Octeontx-pf: Update SGMII mode mapping

Current implementation maps ethtool link modes 10baseT/100baseT/1000baseT
to single firmware mode SGMII. This create a problem for end users who want
to advertise only one speed among them.

This patch addresses the issue by mapping each ethtool link mode
to a corresponding firmware mode also updates new modes supported
by firmware.

Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Link: https://patch.msgid.link/20250625092107.9746-2-hkelam@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
index 971993586fb49da9b6039c52518acc2f3197b618..ac30b6dcb5e5fce358d2c31bd0f94850e8afb6b5 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -1200,16 +1200,16 @@ static void otx2_map_ethtool_link_modes(u64 bitmask,
 {
        switch (bitmask) {
        case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
-               set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
+               set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
                break;
        case  ETHTOOL_LINK_MODE_10baseT_Full_BIT:
-               set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
+               set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
                break;
        case  ETHTOOL_LINK_MODE_100baseT_Half_BIT:
-               set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
+               set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
                break;
        case  ETHTOOL_LINK_MODE_100baseT_Full_BIT:
-               set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
+               set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
                break;
        case  ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
                set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
index d4a27c882a5b90da35599015cc5eb8ffa184c860..da21a6f847cf4790196211518f8e586d57a9da29 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
@@ -95,7 +95,31 @@ enum CGX_MODE_ {
        CGX_MODE_100G_C2M,
        CGX_MODE_100G_CR4,
        CGX_MODE_100G_KR4,
-       CGX_MODE_MAX /* = 29 */
+       CGX_MODE_LAUI_2_C2C_BIT,
+       CGX_MODE_LAUI_2_C2M_BIT,
+       CGX_MODE_50GBASE_CR2_C_BIT,
+       CGX_MODE_50GBASE_KR2_C_BIT,     /* = 30 */
+       CGX_MODE_100GAUI_2_C2C_BIT,
+       CGX_MODE_100GAUI_2_C2M_BIT,
+       CGX_MODE_100GBASE_CR2_BIT,
+       CGX_MODE_100GBASE_KR2_BIT,
+       CGX_MODE_SFI_1G_BIT,
+       CGX_MODE_25GBASE_CR_C_BIT,
+       CGX_MODE_25GBASE_KR_C_BIT,
+       CGX_MODE_SGMII_10M_BIT,
+       CGX_MODE_SGMII_100M_BIT,        /* = 39 */
+       CGX_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */
+       CGX_MODE_5000_BASEX_BIT,
+       CGX_MODE_O_USGMII_BIT,
+       CGX_MODE_Q_USGMII_BIT,
+       CGX_MODE_2_5G_USXGMII_BIT,
+       CGX_MODE_5G_USXGMII_BIT,
+       CGX_MODE_10G_SXGMII_BIT,
+       CGX_MODE_10G_DXGMII_BIT,
+       CGX_MODE_10G_QXGMII_BIT,
+       CGX_MODE_TP_BIT,
+       CGX_MODE_FIBER_BIT,
+       CGX_MODE_MAX /* = 53 */
 };
 /* REQUEST ID types. Input to firmware */
 enum cgx_cmd_id {

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
index 9b7f847b9c226ce8d4a7b6676ab864b0c93100ec..ae1cdd51b9fb3ea3c8ff4cff30050334cd01fe20 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
@@ -15,6 +15,7 @@
 
 #include "otx2_common.h"
 #include "otx2_ptp.h"
+#include <cgx_fw_if.h>
 
 #define DRV_NAME       "rvu-nicpf"
 #define DRV_VF_NAME    "rvu-nicvf"
@@ -1126,17 +1127,9 @@ static void otx2_get_link_mode_info(u64 link_mode_bmap,
                                    *link_ksettings)
 {
        __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) = { 0, };
-       const int otx2_sgmii_features[6] = {
-               ETHTOOL_LINK_MODE_10baseT_Half_BIT,
-               ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-               ETHTOOL_LINK_MODE_100baseT_Half_BIT,
-               ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-               ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
-               ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-       };
        /* CGX link modes to Ethtool link mode mapping */
-       const int cgx_link_mode[27] = {
-               0, /* SGMII  Mode */
+       const int cgx_link_mode[CGX_MODE_MAX] = {
+               0, /* SGMII  1000baseT */
                ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
                ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
                ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
@@ -1166,14 +1159,19 @@ static void otx2_get_link_mode_info(u64 link_mode_bmap,
        };
        u8 bit;
 
-       for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) {
-               /* SGMII mode is set */
-               if (bit == 0)
-                       linkmode_set_bit_array(otx2_sgmii_features,
-                                              ARRAY_SIZE(otx2_sgmii_features),
-                                              otx2_link_modes);
-               else
+       for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, ARRAY_SIZE(cgx_link_mode)) {
+               if (bit == CGX_MODE_SGMII_10M_BIT) {
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, otx2_link_modes);
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, otx2_link_modes);
+               } else if (bit == CGX_MODE_SGMII_100M_BIT) {
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, otx2_link_modes);
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, otx2_link_modes);
+               } else if (bit == CGX_MODE_SGMII) {
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, otx2_link_modes);
+                       linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, otx2_link_modes);
+               } else {
                        linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes);
+               }
        }
 
        if (req_mode == OTX2_MODE_ADVERTISED)