RISC-V: Change CALL macro to use ra as the temporary address register

e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2a5410a61165e6037a8ea1d88f104e53a126c26d..5dfe1661fad1cabe85bfba9c4d1fc587bf385e25 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-01  Michael Clark  <michaeljclark@mac.com>
+
+       * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
+       register.
+
 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 
        * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2b18a1eafe053499ccce46dd7d2587ec7a443438..8343198366e0023ef6f72dadc0cccd164a296911 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"jal",       "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
 {"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
 {"call",      "I",   "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
-{"call",      "I",   "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
+{"call",      "I",   "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
 {"tail",      "I",   "c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
 {"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
 {"nop",       "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },