]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
x86/cpu: Fix #define name for Intel CPU model 0x5A
authorTony Luck <tony.luck@intel.com>
Mon, 7 Oct 2024 16:57:01 +0000 (09:57 -0700)
committerDave Hansen <dave.hansen@linux.intel.com>
Tue, 4 Feb 2025 18:05:53 +0000 (10:05 -0800)
This CPU was mistakenly given the name INTEL_ATOM_AIRMONT_MID. But it
uses a Silvermont core, not Airmont.

Change #define name to INTEL_ATOM_SILVERMONT_MID2

Reported-by: Christian Ludloff <ludloff@gmail.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20241007165701.19693-1-tony.luck%40intel.com
arch/x86/events/intel/core.c
arch/x86/include/asm/intel-family.h
arch/x86/kernel/cpu/common.c
arch/x86/kernel/tsc_msr.c
drivers/powercap/intel_rapl_common.c
drivers/staging/media/atomisp/include/linux/atomisp_platform.h
drivers/thermal/intel/intel_tcc.c
tools/power/x86/turbostat/turbostat.c

index 7601196d1d18e824863f4a84b5e1c0f2e4cce569..89880540ab4344b99eddb1b2f980a668fcabcd13 100644 (file)
@@ -6622,7 +6622,7 @@ __init int intel_pmu_init(void)
        case INTEL_ATOM_SILVERMONT_D:
        case INTEL_ATOM_SILVERMONT_MID:
        case INTEL_ATOM_AIRMONT:
-       case INTEL_ATOM_AIRMONT_MID:
+       case INTEL_ATOM_SILVERMONT_MID2:
                memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));
                memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
index 6d7b04ffc5fd0e41a1b968fcfa81b3ebf78acdc3..8359113e3e58e3619c74d11a9d3a47b9ccc0027b 100644 (file)
 #define INTEL_ATOM_SILVERMONT          IFM(6, 0x37) /* Bay Trail, Valleyview */
 #define INTEL_ATOM_SILVERMONT_D                IFM(6, 0x4D) /* Avaton, Rangely */
 #define INTEL_ATOM_SILVERMONT_MID      IFM(6, 0x4A) /* Merriefield */
+#define INTEL_ATOM_SILVERMONT_MID2     IFM(6, 0x5A) /* Anniedale */
 
 #define INTEL_ATOM_AIRMONT             IFM(6, 0x4C) /* Cherry Trail, Braswell */
-#define INTEL_ATOM_AIRMONT_MID         IFM(6, 0x5A) /* Moorefield */
 #define INTEL_ATOM_AIRMONT_NP          IFM(6, 0x75) /* Lightning Mountain */
 
 #define INTEL_ATOM_GOLDMONT            IFM(6, 0x5C) /* Apollo Lake */
index 7cce91b19fb2c5bf59fb09dd392e6f79c8a55a14..76598a93a8faa6398315e6e377620f783bb39074 100644 (file)
@@ -1164,7 +1164,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 
        VULNWL_INTEL(INTEL_CORE_YONAH,          NO_SSB),
 
-       VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID,    NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
+       VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
        VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP,     NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
 
        VULNWL_INTEL(INTEL_ATOM_GOLDMONT,       NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
index deeb028256709a579eaf9a3ce1a020dcbfb40679..48e6cc1cb017a58895167c3f634d42710ffc2243 100644 (file)
@@ -152,7 +152,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,    &freq_desc_byt),
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID,        &freq_desc_tng),
        X86_MATCH_VFM(INTEL_ATOM_AIRMONT,       &freq_desc_cht),
-       X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID,   &freq_desc_ann),
+       X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,       &freq_desc_ann),
        X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP,    &freq_desc_lgm),
        {}
 };
index 77d75e1f14a9f4ce16fa2832c32794749d84345f..5ccde398231424630f5b76f20f6fa41003d58942 100644 (file)
@@ -1274,7 +1274,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,    &rapl_defaults_byt),
        X86_MATCH_VFM(INTEL_ATOM_AIRMONT,       &rapl_defaults_cht),
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
-       X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID,   &rapl_defaults_ann),
+       X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann),
        X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,      &rapl_defaults_core),
        X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
        X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D,    &rapl_defaults_core),
index 049246774cede9d15b2f47f0989b027502246b1b..6146555fe9cfd859ef0541b79ab04b3a0d08454f 100644 (file)
@@ -172,10 +172,10 @@ void atomisp_unregister_subdev(struct v4l2_subdev *subdev);
 #define IS_BYT __IS_SOC(INTEL_ATOM_SILVERMONT)
 #define IS_CHT __IS_SOC(INTEL_ATOM_AIRMONT)
 #define IS_MRFD        __IS_SOC(INTEL_ATOM_SILVERMONT_MID)
-#define IS_MOFD        __IS_SOC(INTEL_ATOM_AIRMONT_MID)
+#define IS_MOFD        __IS_SOC(INTEL_ATOM_SILVERMONT_MID2)
 
 /* Both CHT and MOFD come with ISP2401 */
 #define IS_ISP2401 __IS_SOCS(INTEL_ATOM_AIRMONT, \
-                            INTEL_ATOM_AIRMONT_MID)
+                            INTEL_ATOM_SILVERMONT_MID2)
 
 #endif /* ATOMISP_PLATFORM_H_ */
index 817421508d5c92465dc403c5bb814d9fab80f227..b2a615aea7c141e63b8cbc513f6966720afba73c 100644 (file)
@@ -106,7 +106,7 @@ static const struct x86_cpu_id intel_tcc_cpu_ids[] __initconst = {
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D,          &temp_broadwell),
        X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID,        &temp_broadwell),
        X86_MATCH_VFM(INTEL_ATOM_AIRMONT,               &temp_broadwell),
-       X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID,           &temp_broadwell),
+       X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,       &temp_broadwell),
        X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP,            &temp_broadwell),
        X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,              &temp_goldmont),
        X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D,            &temp_goldmont),
index 8d5011a0bf60d84a392f635a88017fb01003daf2..26057af6b5a1fc457a06e051636fcbf0e6240384 100644 (file)
@@ -1056,7 +1056,7 @@ static const struct platform_data turbostat_pdata[] = {
         * Missing support for
         * INTEL_ICELAKE
         * INTEL_ATOM_SILVERMONT_MID
-        * INTEL_ATOM_AIRMONT_MID
+        * INTEL_ATOM_SILVERMONT_MID2
         * INTEL_ATOM_AIRMONT_NP
         */
        { 0, NULL },