drm/hisilicon/hibmc: Refactor the member of drm_aux in struct hibmc_dp

Because the drm_aux of struct hibmc_dp_dev's member is not easy to get in
hibmc_drm_dp.c, move the drm_aux to struct hibmc_dp. Then there are some
adaptations and modifications to make this patch compile.

Signed-off-by: Baihan Li <libaihan@huawei.com>
Signed-off-by: Yongbang Shi <shiyongbang@huawei.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250331074212.3370287-5-shiyongbang@huawei.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
index 0a903cce1fa95567e8757be845c20636871ec6b8..ded9e7ce887a11b0293f2d399e4c4aa201fbb54e 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
@@ -8,6 +8,7 @@
 #include <drm/drm_print.h>
 #include "dp_comm.h"
 #include "dp_reg.h"
+#include "dp_hw.h"
 
 #define HIBMC_AUX_CMD_REQ_LEN          GENMASK(7, 4)
 #define HIBMC_AUX_CMD_ADDR             GENMASK(27, 8)
@@ -124,7 +125,8 @@ static int hibmc_dp_aux_parse_xfer(struct hibmc_dp_dev *dp, struct drm_dp_aux_ms
 /* ret >= 0 ,ret is size; ret < 0, ret is err code */
 static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 {
-       struct hibmc_dp_dev *dp = container_of(aux, struct hibmc_dp_dev, aux);
+       struct hibmc_dp *dp_priv = container_of(aux, struct hibmc_dp, aux);
+       struct hibmc_dp_dev *dp = dp_priv->dp_dev;
        u32 aux_cmd;
        int ret;
        u32 val; /* val will be assigned at the beginning of readl_poll_timeout function */
@@ -151,14 +153,15 @@ static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *
        return hibmc_dp_aux_parse_xfer(dp, msg);
 }
 
-void hibmc_dp_aux_init(struct hibmc_dp_dev *dp)
+void hibmc_dp_aux_init(struct hibmc_dp *dp)
 {
-       hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);
-       hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);
-       hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM,
+       hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);
+       hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);
+       hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM,
                                 HIBMC_DP_MIN_PULSE_NUM);
 
        dp->aux.transfer = hibmc_dp_aux_xfer;
        dp->aux.is_remote = 0;
        drm_dp_aux_init(&dp->aux);
+       dp->dp_dev->aux = &dp->aux;
 }

diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h
index e0c6a3b7463b87cadc5c50181c33b354bc8ef77c..4add05c7f161a08b8c301ec1d4143f0fabd7d605 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h
@@ -13,6 +13,8 @@
 #include <linux/io.h>
 #include <drm/display/drm_dp_helper.h>
 
+#include "dp_hw.h"
+
 #define HIBMC_DP_LANE_NUM_MAX 2
 
 struct hibmc_link_status {
@@ -32,7 +34,7 @@ struct hibmc_dp_link {
 };
 
 struct hibmc_dp_dev {
-       struct drm_dp_aux aux;
+       struct drm_dp_aux *aux;
        struct drm_device *dev;
        void __iomem *base;
        struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field() */
@@ -58,7 +60,7 @@ struct hibmc_dp_dev {
                mutex_unlock(&_dp->lock);                               \
        } while (0)
 
-void hibmc_dp_aux_init(struct hibmc_dp_dev *dp);
+void hibmc_dp_aux_init(struct hibmc_dp *dp);
 int hibmc_dp_link_training(struct hibmc_dp_dev *dp);
 int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp);
 int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp);

diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
index dcb2ab5ea6bb80265b076e3a3bf28d7f68770c96..aa9354a996c9a9ef9501bc0dbff07dc816f88427 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
@@ -167,7 +167,7 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp)
        dp_dev->dev = drm_dev;
        dp_dev->base = dp->mmio + HIBMC_DP_OFFSET;
 
-       hibmc_dp_aux_init(dp_dev);
+       hibmc_dp_aux_init(dp);
 
        ret = hibmc_dp_serdes_init(dp_dev);
        if (ret)

diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
index 4dc13b3d9875f4c98bb0aae5c2081354576b5ad4..53b6d0beecea0a054bef890d66ce16b5abb37d60 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
@@ -10,6 +10,7 @@
 #include <drm/drm_encoder.h>
 #include <drm/drm_connector.h>
 #include <drm/drm_print.h>
+#include <drm/display/drm_dp_helper.h>
 
 struct hibmc_dp_dev;
 
@@ -19,6 +20,7 @@ struct hibmc_dp {
        struct drm_encoder encoder;
        struct drm_connector connector;
        void __iomem *mmio;
+       struct drm_dp_aux aux;
 };
 
 int hibmc_dp_hw_init(struct hibmc_dp *dp);

diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
index 61397852957156d15ab49d4192f07c530532b900..74f7832ea53eaef4f9e784447bb609f9949ebd15 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
@@ -42,7 +42,7 @@ static int hibmc_dp_link_training_configure(struct hibmc_dp_dev *dp)
        /* set rate and lane count */
        buf[0] = dp->link.cap.link_rate;
        buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes;
-       ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
+       ret = drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
        if (ret != sizeof(buf)) {
                drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret);
                return ret >= 0 ? -EIO : ret;
@@ -51,7 +51,7 @@ static int hibmc_dp_link_training_configure(struct hibmc_dp_dev *dp)
        /* set 8b/10b and downspread */
        buf[0] = DP_SPREAD_AMP_0_5;
        buf[1] = DP_SET_ANSI_8B10B;
-       ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));
+       ret = drm_dp_dpcd_write(dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));
        if (ret != sizeof(buf)) {
                drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n", ret);
                return ret >= 0 ? -EIO : ret;
@@ -96,7 +96,7 @@ static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev *dp, int pattern)
 
        hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, val);
 
-       ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(buf));
+       ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(buf));
        if (ret != sizeof(buf)) {
                drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n");
                return ret >= 0 ? -EIO : ret;
@@ -126,7 +126,7 @@ static int hibmc_dp_link_training_cr_pre(struct hibmc_dp_dev *dp)
        if (ret)
                return ret;
 
-       ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes);
+       ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes);
        if (ret != dp->link.cap.lanes) {
                drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n");
                return ret >= 0 ? -EIO : ret;
@@ -210,9 +210,9 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_dev *dp)
 
        voltage_tries = 1;
        for (cr_tries = 0; cr_tries < 80; cr_tries++) {
-               drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
+               drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd);
 
-               ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status);
+               ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status);
                if (ret) {
                        drm_err(dp->dev, "Get lane status failed\n");
                        return ret;
@@ -236,7 +236,7 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_dev *dp)
                if (ret)
                        return ret;
 
-               ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set,
+               ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set,
                                        dp->link.cap.lanes);
                if (ret != dp->link.cap.lanes) {
                        drm_dbg_dp(dp->dev, "Update link training failed\n");
@@ -263,9 +263,9 @@ static int hibmc_dp_link_training_channel_eq(struct hibmc_dp_dev *dp)
                return ret;
 
        for (eq_tries = 0; eq_tries < HIBMC_EQ_MAX_RETRY; eq_tries++) {
-               drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
+               drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd);
 
-               ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status);
+               ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status);
                if (ret) {
                        drm_err(dp->dev, "get lane status failed\n");
                        break;
@@ -290,7 +290,7 @@ static int hibmc_dp_link_training_channel_eq(struct hibmc_dp_dev *dp)
                if (ret)
                        return ret;
 
-               ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
+               ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET,
                                        dp->link.train_set, dp->link.cap.lanes);
                if (ret != dp->link.cap.lanes) {
                        drm_dbg_dp(dp->dev, "Update link training failed\n");
@@ -330,7 +330,7 @@ int hibmc_dp_link_training(struct hibmc_dp_dev *dp)
        struct hibmc_dp_link *link = &dp->link;
        int ret;
 
-       ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd);
+       ret = drm_dp_read_dpcd_caps(dp->aux, dp->dpcd);
        if (ret)
                drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret);