ARM: dts: imx6qdl: add boot phase properties

dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

All SoCs require buses (aips and spba), clock, iomuxc, ipu and
SOC access during boot process.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index 6b430fcc9fccf6c21fa517a81db23ff0b954daf9..4dc2c410cf61321477d53964d0071c35f90fd763 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -161,6 +161,7 @@
                compatible = "simple-bus";
                interrupt-parent = <&gpc>;
                ranges;
+               bootph-all;
 
                dma_apbh: dma-controller@110000 {
                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -309,6 +310,7 @@
                        #size-cells = <1>;
                        reg = <0x02000000 0x100000>;
                        ranges;
+                       bootph-pre-ram;
 
                        spba-bus@2000000 {
                                compatible = "fsl,spba-bus", "simple-bus";
@@ -316,6 +318,7 @@
                                #size-cells = <1>;
                                reg = <0x02000000 0x40000>;
                                ranges;
+                               bootph-pre-ram;
 
                                spdif: spdif@2004000 {
                                        compatible = "fsl,imx35-spdif";
@@ -932,6 +935,7 @@
                        iomuxc: pinctrl@20e0000 {
                                compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
                                reg = <0x20e0000 0x4000>;
+                               bootph-pre-ram;
                        };
 
                        dcic1: dcic@20e4000 {
@@ -962,6 +966,7 @@
                        #size-cells = <1>;
                        reg = <0x02100000 0x100000>;
                        ranges;
+                       bootph-pre-ram;
 
                        crypto: crypto@2100000 {
                                compatible = "fsl,sec-v4.0";
@@ -1332,6 +1337,7 @@
                                 <&clks IMX6QDL_CLK_IPU1_DI1>;
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 2>;
+                       bootph-all;
 
                        ipu1_csi0: port@0 {
                                reg = <0>;