--- /dev/null
+From 15239099d7a7a9ecdc1ccb5b187ae4cda5488ff9 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Tue, 5 Mar 2013 09:50:58 +0100
+Subject: drm/i915: enable irqs earlier when resuming
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 15239099d7a7a9ecdc1ccb5b187ae4cda5488ff9 upstream.
+
+We need it to restore the ilk rc6 context, since the gpu wait no
+requires interrupts. But in general having interrupts around should
+help in code sanity, since more and more stuff is interrupt driven.
+
+This regression has been introduced in
+
+commit 3e9605018ab3e333d51cc90fccfde2031886763b
+Author: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Tue Nov 27 16:22:54 2012 +0000
+
+ drm/i915: Rearrange code to only have a single method for waiting upon the ring
+
+Like in the driver load code we need to make sure that hotplug
+interrupts don't cause havoc with our modeset state, hence block them
+with the existing infrastructure. Again we ignore races where we might
+loose hotplug interrupts ...
+
+Note that the driver load part of the regression has already been
+fixed in
+
+commit 52d7ecedac3f96fb562cb482c139015372728638
+Author: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Sat Dec 1 21:03:22 2012 +0100
+
+ drm/i915: reorder setup sequence to have irqs for output setup
+
+v2: Add a note to the commit message about which patch fixed the
+driver load part of the regression. Stable kernels need to backport
+both patches.
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=54691
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@intel.com>
+Reported-and-Tested-by: Ilya Tumaykin <itumaykin@gmail.com>
+Reviewed-by: Chris wilson <chris@chris-wilson.co.uk> (v1)
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -486,6 +486,7 @@ static int i915_drm_freeze(struct drm_de
+ intel_modeset_disable(dev);
+
+ drm_irq_uninstall(dev);
++ dev_priv->enable_hotplug_processing = false;
+ }
+
+ i915_save_state(dev);
+@@ -562,9 +563,19 @@ static int __i915_drm_thaw(struct drm_de
+ error = i915_gem_init_hw(dev);
+ mutex_unlock(&dev->struct_mutex);
+
++ /* We need working interrupts for modeset enabling ... */
++ drm_irq_install(dev);
++
+ intel_modeset_init_hw(dev);
+ intel_modeset_setup_hw_state(dev, false);
+- drm_irq_install(dev);
++
++ /*
++ * ... but also need to make sure that hotplug processing
++ * doesn't cause havoc. Like in the driver load code we don't
++ * bother with the tiny race here where we might loose hotplug
++ * notifications.
++ * */
++ dev_priv->enable_hotplug_processing = true;
+ }
+
+ intel_opregion_init(dev);
--- /dev/null
+From 86c268ed0f9b3b4d51d81dd8fcec533a164414d1 Mon Sep 17 00:00:00 2001
+From: Kenneth Graunke <kenneth@whitecape.org>
+Date: Fri, 1 Mar 2013 17:00:50 -0800
+Subject: drm/i915: Fix Haswell/CRW PCI IDs.
+
+From: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 86c268ed0f9b3b4d51d81dd8fcec533a164414d1 upstream.
+
+The second digit was off by one, which meant we accidentally treated
+GT(n) as GT(n-1). This also meant no support for GT1 at all.
+
+Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -377,15 +377,15 @@ static const struct pci_device_id pciidl
+ INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
+ INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
+ INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+- INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
++ INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
++ INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
+ INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+- INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
+- INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
++ INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
++ INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
+ INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+- INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
+- INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
++ INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
++ INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
+ INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+- INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
+ INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+ INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
+ INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
--- /dev/null
+From 52d7ecedac3f96fb562cb482c139015372728638 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Sat, 1 Dec 2012 21:03:22 +0100
+Subject: drm/i915: reorder setup sequence to have irqs for output setup
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 52d7ecedac3f96fb562cb482c139015372728638 upstream.
+
+Otherwise the new&shiny irq-driven gmbus and dp aux code won't work that
+well. Noticed since the dp aux code doesn't have an automatic fallback
+with a timeout (since the hw provides for that already).
+
+v2: Simple move drm_irq_install before intel_modeset_gem_init, as
+suggested by Ben Widawsky.
+
+v3: Now that interrupts are enabled before all connectors are fully
+set up, we might fall over serving a HPD interrupt while things are
+still being set up. Instead of jumping through massive hoops and
+complicating the code with a separate hpd irq enable step, simply
+block out the hotplug work item from doing anything until things are
+in place.
+
+v4: Actually, we can enable hotplug processing only after the fbdev is
+fully set up, since we call down into the fbdev from the hotplug work
+functions. So stick the hpd enabling right next to the poll helper
+initialization.
+
+v5: We need to enable irqs before intel_modeset_init, since that
+function sets up the outputs.
+
+v6: Fixup cleanup sequence, too.
+
+Reviewed-by: Imre Deak <imre.deak@intel.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_dma.c | 23 ++++++++++++++---------
+ drivers/gpu/drm/i915/i915_drv.h | 1 +
+ drivers/gpu/drm/i915/i915_irq.c | 4 ++++
+ 3 files changed, 19 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_dma.c
++++ b/drivers/gpu/drm/i915/i915_dma.c
+@@ -1297,19 +1297,21 @@ static int i915_load_modeset_init(struct
+ if (ret)
+ goto cleanup_vga_switcheroo;
+
++ ret = drm_irq_install(dev);
++ if (ret)
++ goto cleanup_gem_stolen;
++
++ /* Important: The output setup functions called by modeset_init need
++ * working irqs for e.g. gmbus and dp aux transfers. */
+ intel_modeset_init(dev);
+
+ ret = i915_gem_init(dev);
+ if (ret)
+- goto cleanup_gem_stolen;
+-
+- intel_modeset_gem_init(dev);
++ goto cleanup_irq;
+
+ INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
+
+- ret = drm_irq_install(dev);
+- if (ret)
+- goto cleanup_gem;
++ intel_modeset_gem_init(dev);
+
+ /* Always safe in the mode setting case. */
+ /* FIXME: do pre/post-mode set stuff in core KMS code */
+@@ -1317,7 +1319,10 @@ static int i915_load_modeset_init(struct
+
+ ret = intel_fbdev_init(dev);
+ if (ret)
+- goto cleanup_irq;
++ goto cleanup_gem;
++
++ /* Only enable hotplug handling once the fbdev is fully set up. */
++ dev_priv->enable_hotplug_processing = true;
+
+ drm_kms_helper_poll_init(dev);
+
+@@ -1326,13 +1331,13 @@ static int i915_load_modeset_init(struct
+
+ return 0;
+
+-cleanup_irq:
+- drm_irq_uninstall(dev);
+ cleanup_gem:
+ mutex_lock(&dev->struct_mutex);
+ i915_gem_cleanup_ringbuffer(dev);
+ mutex_unlock(&dev->struct_mutex);
+ i915_gem_cleanup_aliasing_ppgtt(dev);
++cleanup_irq:
++ drm_irq_uninstall(dev);
+ cleanup_gem_stolen:
+ i915_gem_cleanup_stolen(dev);
+ cleanup_vga_switcheroo:
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -672,6 +672,7 @@ typedef struct drm_i915_private {
+
+ u32 hotplug_supported_mask;
+ struct work_struct hotplug_work;
++ bool enable_hotplug_processing;
+
+ int num_pipe;
+ int num_pch_pll;
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -287,6 +287,10 @@ static void i915_hotplug_work_func(struc
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct intel_encoder *encoder;
+
++ /* HPD irq before everything is fully set up. */
++ if (!dev_priv->enable_hotplug_processing)
++ return;
++
+ mutex_lock(&mode_config->mutex);
+ DRM_DEBUG_KMS("running encoder hotplug functions\n");
+
--- /dev/null
+From f40ebd6bcbbd0d30591f42dc16be52b5086a366b Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Tue, 5 Mar 2013 14:24:48 +0100
+Subject: drm/i915: Turn off hsync and vsync on ADPA when disabling crt
+
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+
+commit f40ebd6bcbbd0d30591f42dc16be52b5086a366b upstream.
+
+According to PRM we need to disable hsync and vsync even though ADPA is
+disabled. The previous code did infact do the opposite so we fix it.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
+Tested-by: max <manikulin@gmail.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_crt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_crt.c
++++ b/drivers/gpu/drm/i915/intel_crt.c
+@@ -88,7 +88,7 @@ static void intel_disable_crt(struct int
+ u32 temp;
+
+ temp = I915_READ(crt->adpa_reg);
+- temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
++ temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
+ temp &= ~ADPA_DAC_ENABLE;
+ I915_WRITE(crt->adpa_reg, temp);
+ }
arm-7659-1-mm-make-mm-context.id-an-atomic64_t-variable.patch
arm-7663-1-perf-fix-armv7-evtype_mask-to-include-nsh-bit.patch
drm-i915-increase-the-rc6p-threshold.patch
+drm-i915-fix-haswell-crw-pci-ids.patch
+drm-i915-reorder-setup-sequence-to-have-irqs-for-output-setup.patch
+drm-i915-enable-irqs-earlier-when-resuming.patch
+drm-i915-turn-off-hsync-and-vsync-on-adpa-when-disabling-crt.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
