[AArch64] Backport support id_mmfr4 system register

2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	Applied from master
	2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	opcode/
	  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

	gas/testsuite/
	  * sysreg.d: Add id_mmfr4_el1, update expected output.
	  * sysreg.s: Add id_mmfr4_el1.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6477054fcf325cc1358201dfc741fa100adfe248..bc581b9e8ccc223d1cd1c097e0b1de877075fb83 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       Applied from master.
+       2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * sysreg.d: Add id_mmfr4_el1, update expected output.
+       * sysreg.s: Add id_mmfr4_el1.
+
 2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
 
        * gas/aarch64/codealign.d: Add test for code section alignment.

diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d
index 7795b4dd30ea360249c2162a251014184d9adad4..157340cd5a109f69b36b976e54d3107c3648a6c0 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg.d
@@ -17,14 +17,15 @@ Disassembly of section \.text:
   24:  d53801a0        mrs     x0, id_mmfr1_el1
   28:  d53801c0        mrs     x0, id_mmfr2_el1
   2c:  d53801e0        mrs     x0, id_mmfr3_el1
-  30:  d5380200        mrs     x0, id_isar0_el1
-  34:  d5380220        mrs     x0, id_isar1_el1
-  38:  d5380240        mrs     x0, id_isar2_el1
-  3c:  d5380260        mrs     x0, id_isar3_el1
-  40:  d5380280        mrs     x0, id_isar4_el1
-  44:  d53802a0        mrs     x0, id_isar5_el1
-  48:  d538cc00        mrs     x0, s3_0_c12_c12_0
-  4c:  d5384600        mrs     x0, s3_0_c4_c6_0
-  50:  d5184600        msr     s3_0_c4_c6_0, x0
-  54:  d5310300        mrs     x0, s2_1_c0_c3_0
-  58:  d5110300        msr     s2_1_c0_c3_0, x0
+  30:  d53802c0        mrs     x0, id_mmfr4_el1
+  34:  d5380200        mrs     x0, id_isar0_el1
+  38:  d5380220        mrs     x0, id_isar1_el1
+  3c:  d5380240        mrs     x0, id_isar2_el1
+  40:  d5380260        mrs     x0, id_isar3_el1
+  44:  d5380280        mrs     x0, id_isar4_el1
+  48:  d53802a0        mrs     x0, id_isar5_el1
+  4c:  d538cc00        mrs     x0, s3_0_c12_c12_0
+  50:  d5384600        mrs     x0, s3_0_c4_c6_0
+  54:  d5184600        msr     s3_0_c4_c6_0, x0
+  58:  d5310300        mrs     x0, s2_1_c0_c3_0
+  5c:  d5110300        msr     s2_1_c0_c3_0, x0

diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s
index b7e5ff6ca1f64858c8da46dc8591246910491ebd..897467409c48de6af3483d91d03ede85427417bc 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg.s
@@ -16,6 +16,7 @@
        mrs x0, id_mmfr1_el1
        mrs x0, id_mmfr2_el1
        mrs x0, id_mmfr3_el1
+       mrs x0, id_mmfr4_el1
        mrs x0, id_isar0_el1
        mrs x0, id_isar1_el1
        mrs x0, id_isar2_el1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2d01f5ab480b5285f82ce495ee40101c4fe4d62f..53afdd2c93df4953901ca22493cad23808e64d74 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       Applied from master
+       2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
+
 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 
        Applied from master.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 430cf5bcd98b968caf31ea99bba43aa1e02a4c32..e168b9dc60f62af337cd7ebbded7a92afd3147fa 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2765,6 +2765,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "id_mmfr1_el1",     CPENC(3,0,C0,C1,5),    0 }, /* RO */
   { "id_mmfr2_el1",     CPENC(3,0,C0,C1,6),    0 }, /* RO */
   { "id_mmfr3_el1",     CPENC(3,0,C0,C1,7),    0 }, /* RO */
+  { "id_mmfr4_el1",     CPENC(3,0,C0,C2,6),    0 }, /* RO */
   { "id_isar0_el1",     CPENC(3,0,C0,C2,0),    0 }, /* RO */
   { "id_isar1_el1",     CPENC(3,0,C0,C2,1),    0 }, /* RO */
   { "id_isar2_el1",     CPENC(3,0,C0,C2,2),    0 }, /* RO */