]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
4.19-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 2 Dec 2019 16:26:35 +0000 (17:26 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 2 Dec 2019 16:26:35 +0000 (17:26 +0100)
added patches:
clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
clk-at91-generated-set-audio_pll_allowed-in-at91_clk_register_generated.patch
usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch

queue-4.19/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch [new file with mode: 0644]
queue-4.19/clk-at91-generated-set-audio_pll_allowed-in-at91_clk_register_generated.patch [new file with mode: 0644]
queue-4.19/series
queue-4.19/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch [new file with mode: 0644]

diff --git a/queue-4.19/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch b/queue-4.19/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
new file mode 100644 (file)
index 0000000..5e3509b
--- /dev/null
@@ -0,0 +1,38 @@
+From 263eaf8f172d9f44e15d6aca85fe40ec18d2c477 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <eugen.hristev@microchip.com>
+Date: Mon, 9 Sep 2019 15:30:31 +0000
+Subject: clk: at91: fix update bit maps on CFG_MOR write
+
+From: Eugen Hristev <eugen.hristev@microchip.com>
+
+commit 263eaf8f172d9f44e15d6aca85fe40ec18d2c477 upstream.
+
+The regmap update bits call was not selecting the proper mask, considering
+the bits which was updating.
+Update the mask from call to also include OSCBYPASS.
+Removed MOSCEN which was not updated.
+
+Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally")
+Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
+Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com
+Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/at91/clk-main.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/at91/clk-main.c
++++ b/drivers/clk/at91/clk-main.c
+@@ -162,7 +162,7 @@ at91_clk_register_main_osc(struct regmap
+       if (bypass)
+               regmap_update_bits(regmap,
+                                  AT91_CKGR_MOR, MOR_KEY_MASK |
+-                                 AT91_PMC_MOSCEN,
++                                 AT91_PMC_OSCBYPASS,
+                                  AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
+       hw = &osc->hw;
diff --git a/queue-4.19/clk-at91-generated-set-audio_pll_allowed-in-at91_clk_register_generated.patch b/queue-4.19/clk-at91-generated-set-audio_pll_allowed-in-at91_clk_register_generated.patch
new file mode 100644 (file)
index 0000000..c6353ac
--- /dev/null
@@ -0,0 +1,91 @@
+From c1e4580a1d0ff510d56268c1fc7fcfeec366fe70 Mon Sep 17 00:00:00 2001
+From: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Date: Tue, 16 Oct 2018 16:21:43 +0200
+Subject: clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()
+
+From: Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+commit c1e4580a1d0ff510d56268c1fc7fcfeec366fe70 upstream.
+
+Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it
+easier to do it from code that is not parsing device tree.
+
+Also, this fixes an issue where the resulting clk_hw can be dereferenced
+before being tested for error.
+
+Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate")
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/at91/clk-generated.c |   28 ++++++++++------------------
+ 1 file changed, 10 insertions(+), 18 deletions(-)
+
+--- a/drivers/clk/at91/clk-generated.c
++++ b/drivers/clk/at91/clk-generated.c
+@@ -284,7 +284,7 @@ static void clk_generated_startup(struct
+ static struct clk_hw * __init
+ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
+                           const char *name, const char **parent_names,
+-                          u8 num_parents, u8 id,
++                          u8 num_parents, u8 id, bool pll_audio,
+                           const struct clk_range *range)
+ {
+       struct clk_generated *gck;
+@@ -308,6 +308,7 @@ at91_clk_register_generated(struct regma
+       gck->regmap = regmap;
+       gck->lock = lock;
+       gck->range = *range;
++      gck->audio_pll_allowed = pll_audio;
+       clk_generated_startup(gck);
+       hw = &gck->hw;
+@@ -333,7 +334,6 @@ static void __init of_sama5d2_clk_genera
+       struct device_node *gcknp;
+       struct clk_range range = CLK_RANGE(0, 0);
+       struct regmap *regmap;
+-      struct clk_generated *gck;
+       num_parents = of_clk_get_parent_count(np);
+       if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
+@@ -350,6 +350,8 @@ static void __init of_sama5d2_clk_genera
+               return;
+       for_each_child_of_node(np, gcknp) {
++              bool pll_audio = false;
++
+               if (of_property_read_u32(gcknp, "reg", &id))
+                       continue;
+@@ -362,24 +364,14 @@ static void __init of_sama5d2_clk_genera
+               of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
+                                     &range);
++              if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
++                  (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
++                   id == GCK_ID_CLASSD))
++                      pll_audio = true;
++
+               hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
+                                                 parent_names, num_parents,
+-                                                id, &range);
+-
+-              gck = to_clk_generated(hw);
+-
+-              if (of_device_is_compatible(np,
+-                                          "atmel,sama5d2-clk-generated")) {
+-                      if (gck->id == GCK_ID_SSC0 || gck->id == GCK_ID_SSC1 ||
+-                          gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
+-                          gck->id == GCK_ID_CLASSD)
+-                              gck->audio_pll_allowed = true;
+-                      else
+-                              gck->audio_pll_allowed = false;
+-              } else {
+-                      gck->audio_pll_allowed = false;
+-              }
+-
++                                                id, pll_audio, &range);
+               if (IS_ERR(hw))
+                       continue;
index 2adf5be325f388ad61e43ae9d999a7336f9a5fe6..e36ad5a6e0b011e1e0626bf89e4cf430f286a91a 100644 (file)
@@ -264,3 +264,6 @@ mtd-remove-a-debug-trace-in-mtdpart.c.patch
 mm-gup-add-missing-refcount-overflow-checks-on-s390.patch
 kvm-nvmx-rename-enter_vmx_non_root_mode-to-nested_vmx_enter_non_root_mode.patch
 kvm-nvmx-assimilate-nested_vmx_entry_failure-into-nested_vmx_enter_non_root_mode.patch
+clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
+clk-at91-generated-set-audio_pll_allowed-in-at91_clk_register_generated.patch
+usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch
diff --git a/queue-4.19/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch b/queue-4.19/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch
new file mode 100644 (file)
index 0000000..354501a
--- /dev/null
@@ -0,0 +1,40 @@
+From 6689f0f4bb14e50917ba42eb9b41c25e0184970c Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Sun, 7 Jul 2019 16:22:01 +0200
+Subject: usb: dwc2: use a longer core rest timeout in dwc2_core_reset()
+
+From: Mathias Kresin <dev@kresin.me>
+
+commit 6689f0f4bb14e50917ba42eb9b41c25e0184970c upstream.
+
+Testing on different generations of Lantiq MIPS SoC based boards, showed
+that it takes up to 1500 us until the core reset bit is cleared.
+
+The driver from the vendor SDK (ifxhcd) uses a 1 second timeout. Use the
+same timeout to fix wrong hang detections and make the driver work for
+Lantiq MIPS SoCs.
+
+At least till kernel 4.14 the hanging reset only caused a warning but
+the driver was probed successful. With kernel 4.19 errors out with
+EBUSY.
+
+Cc: linux-stable <stable@vger.kernel.org> # 4.19+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/dwc2/core.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -524,7 +524,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
+       greset |= GRSTCTL_CSFTRST;
+       dwc2_writel(hsotg, greset, GRSTCTL);
+-      if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
++      if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 10000)) {
+               dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
+                        __func__);
+               return -EBUSY;