drm/i915/guc: prevent a possible int overflow in wq offsets

It may be possible for the sum of the values derived from
i915_ggtt_offset() and __get_parent_scratch_offset()/
i915_ggtt_offset() to go over the u32 limit before being assigned
to wq offsets of u64 type.

Mitigate these issues by expanding one of the right operands
to u64 to avoid any overflow issues just in case.

Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.

Fixes: c2aa552ff09d ("drm/i915/guc: Add multi-lrc context registration")
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
Link: https://patchwork.freedesktop.org/patch/msgid/20240725155925.14707-1-n.zhandarovich@fintech.ru
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8322c913bc3cacb286ed3d83769466600fb0d22a..ed979847187f5322cea11f1bdce9371086d92c03 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2843,9 +2843,9 @@ static void prepare_context_registration_info_v70(struct intel_context *ce,
                ce->parallel.guc.wqi_tail = 0;
                ce->parallel.guc.wqi_head = 0;
 
-               wq_desc_offset = i915_ggtt_offset(ce->state) +
+               wq_desc_offset = (u64)i915_ggtt_offset(ce->state) +
                                 __get_parent_scratch_offset(ce);
-               wq_base_offset = i915_ggtt_offset(ce->state) +
+               wq_base_offset = (u64)i915_ggtt_offset(ce->state) +
                                 __get_wq_offset(ce);
                info->wq_desc_lo = lower_32_bits(wq_desc_offset);
                info->wq_desc_hi = upper_32_bits(wq_desc_offset);