RISC-V: testsuite: Skip test with -flto

Hi,

the zbb-rol-ror and stack_save_restore tests use the -fno-lto option and
scan the final assembly.  For an invocation like -flto ... -fno-lto the
output file we scan is still something like
  zbb-rol-ror-09.ltrans0.ltrans.s.

Therefore skip the tests when "-flto" is present.  This gets rid
of a few UNRESOLVED tests.

Regtested on rv64gcv_zvl512b.  Going to push if the CI agrees.

Regards
 Robin

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/stack_save_restore_1.c: Skip for -flto.
	* gcc.target/riscv/stack_save_restore_2.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-04.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-05.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-06.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-07.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-08.c: Ditto.
	* gcc.target/riscv/zbb-rol-ror-09.c: Ditto.

diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
index d8b0668a820fe72e401aa9be21adbf7cb13f3f9b..e0a7c68760a98f313fd46ad8adadf38282eb806e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto" } */
+/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 char my_getchar();

diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
index 5f0389243b1fafb3127f79fdfa0d69bdc2fe0ff2..aadeaa58230569862cb20e65c2387f425b47bf39 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto" } */
+/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 char my_getchar();

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
index 28350e5e93717837ea1f7f545a35c97a0f7c2193..b413b10ea931acccf90b6fa86b745c20f04bdaa6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
index cc44653acfbd75fe2d59d307f273a6db471fb593..179477ed93b89159180d6c31886b7dc2eb5ac813 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
index 7a98a5712bfe89e2625b3268cd1fd9b15e40de2b..b5f0b8b9027cfca49102a009a55d5424284ef64d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
index a08a9eb772e221eec3455e93205bfc1ce7076249..037230625fb723afc821380eb0c711196407a157 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
index bf19b76b431dce69e781edd3984b3fcb2f1a6463..b3864e72ca673f9ebcee2ff176e9d081703815ed 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
index 5c4b9f58de134cc609606aad207436d296c913f9..121dca90d12712cc3c50b0e6e800490030ef0284 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 /* { dg-final { scan-assembler-not {\mand} } } */