arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.

It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644 (file)
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += axiado
 subdir-y += bitmain
 subdir-y += blaize
 subdir-y += broadcom

diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644 (file)
index 0000000..6676ad0
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb

diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
new file mode 100644 (file)
index 0000000..92101c5
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+       model = "Axiado AX3000 EVK";
+       compatible = "axiado,ax3000-evk", "axiado,ax3000";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               serial3 = &uart3;
+       };
+
+       chosen {
+               stdout-path = "serial3:115200";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               /* Cortex-A53 will use following memory map */
+               reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
+                     <0x00000004 0x00000000 0x00000000 0x80000000>;
+       };
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&gpio3 {
+       status = "okay";
+};
+
+&gpio4 {
+       status = "okay";
+};
+
+&gpio5 {
+       status = "okay";
+};
+
+&gpio6 {
+       status = "okay";
+};
+
+&gpio7 {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&uart3 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644 (file)
index 0000000..792f52e
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008;    /* cpu-release-addr */
+/ {
+       model = "Axiado AX3000";
+       interrupt-parent = <&gic500>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x3c0013a0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x1>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x3c0013a0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x2>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x3c0013a0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x3>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x3c0013a0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&l2>;
+               };
+
+               l2: l2-cache0 {
+                       compatible = "cache";
+                       cache-size = <0x100000>;
+                       cache-unified;
+                       cache-line-size = <64>;
+                       cache-sets = <1024>;
+                       cache-level = <2>;
+               };
+       };
+
+       clocks {
+               clk_xin: clock-200000000 {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+                       clock-output-names = "clk_xin";
+               };
+
+               refclk: clock-125000000 {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <125000000>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               ranges;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               interrupt-parent = <&gic500>;
+
+               gic500: interrupt-controller@80300000 {
+                       compatible = "arm,gic-v3";
+                       reg = <0x00 0x80300000 0x00 0x10000>,
+                             <0x00 0x80380000 0x00 0x80000>;
+                       ranges;
+                       #interrupt-cells = <3>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       interrupt-controller;
+                       #redistributor-regions = <1>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               /* GPIO Controller banks 0 - 7 */
+               gpio0: gpio-controller@80500000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80500000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio1: gpio-controller@80580000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80580000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio2: gpio-controller@80600000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80600000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio3: gpio-controller@80680000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80680000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio4: gpio-controller@80700000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80700000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio5: gpio-controller@80780000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80780000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio6: gpio-controller@80800000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80800000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio7: gpio-controller@80880000 {
+                       compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+                       reg = <0x00 0x80880000 0x00 0x400>;
+                       clocks = <&refclk>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
+               /* I3C Controller 0 - 16 */
+               i3c0: i3c@80500400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80500400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c1: i3c@80500800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80500800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c2: i3c@80580400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80580400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c3: i3c@80580800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80580800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c4: i3c@80600400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80600400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c5: i3c@80600800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80600800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c6: i3c@80680400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80680400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c7: i3c@80680800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80680800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c8: i3c@80700400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80700400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c9: i3c@80700800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80700800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c10: i3c@80780400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80780400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c11: i3c@80780800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80780800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c12: i3c@80800400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80800400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c13: i3c@80800800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80800800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c14: i3c@80880400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80880400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c15: i3c@80880800 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80880800 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i3c16: i3c@80620400 {
+                       compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+                       reg = <0x00 0x80620400 0x00 0x400>;
+                       clocks = <&refclk &clk_xin>;
+                       clock-names = "pclk", "sysclk";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       i2c-scl-hz = <100000>;
+                       i3c-scl-hz = <400000>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               uart0: serial@80520000 {
+                       compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+                       reg = <0x00 0x80520000 0x00 0x100>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "uart_clk", "pclk";
+                       clocks = <&refclk &refclk>;
+                       status = "disabled";
+               };
+
+               uart1: serial@805a0000 {
+                       compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+                       reg = <0x00 0x805A0000 0x00 0x100>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "uart_clk", "pclk";
+                       clocks = <&refclk &refclk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@80620000 {
+                       compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+                       reg = <0x00 0x80620000 0x00 0x100>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "uart_clk", "pclk";
+                       clocks = <&refclk &refclk>;
+                       status = "disabled";
+               };
+
+               uart3: serial@80520800 {
+                       compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+                       reg = <0x00 0x80520800 0x00 0x100>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "uart_clk", "pclk";
+                       clocks = <&refclk &refclk>;
+                       status = "disabled";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupt-parent = <&gic500>;
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};