drm/amd/display: add clear_tiling hubp callbacks

This adds clear_tiling callbacks to the hubp structure that
will be used for drm panic support to clear the tiling on
a display.  hubp3 support from Jocelyn's original patch
and the rest from me.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Lu Yao <yaolu@kylinos.cn>
Cc: Jocelyn Falempe <jfalempe@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index 22ac2b7e49aeae66e6ce182f77be943df14151f4..f0ba944553df596cd2550cd107d06557b095d95e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -518,6 +518,20 @@ bool hubp1_program_surface_flip_and_addr(
        return true;
 }
 
+void hubp1_clear_tiling(struct hubp *hubp)
+{
+       struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+       REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
+       REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
+
+       REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                    PRIMARY_SURFACE_DCC_EN, 0,
+                    PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
+                    SECONDARY_SURFACE_DCC_EN, 0,
+                    SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
+}
+
 void hubp1_dcc_control(struct hubp *hubp, bool enable,
                enum hubp_ind_block_size independent_64b_blks)
 {
@@ -1363,6 +1377,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
        .hubp_disable_control =  hubp1_disable_control,
        .hubp_get_underflow_status = hubp1_get_underflow_status,
        .hubp_init = hubp1_init,
+       .hubp_clear_tiling = hubp1_clear_tiling,
 
        .dmdata_set_attributes = NULL,
        .dmdata_load = NULL,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
index 69119b2fdce23b878f9148e62cfa37a7820ac30f..631350cd4f2ed6963d53dcced67f2edda1c60024 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
@@ -794,4 +794,6 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset);
 
 void hubp1_set_flip_int(struct hubp *hubp);
 
+void hubp1_clear_tiling(struct hubp *hubp);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index 0637e4c552d8a29cda4bb087b391b2d6d7305805..200194544bf0c25c0b36c4aa87f2cb9ea181d5f2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -406,6 +406,20 @@ void hubp2_program_rotation(
                                H_MIRROR_EN, mirror);
 }
 
+void hubp2_clear_tiling(struct hubp *hubp)
+{
+       struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+       REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
+       REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
+
+       REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                    PRIMARY_SURFACE_DCC_EN, 0,
+                    PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
+                    SECONDARY_SURFACE_DCC_EN, 0,
+                    SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
+}
+
 void hubp2_dcc_control(struct hubp *hubp, bool enable,
                enum hubp_ind_block_size independent_64b_blks)
 {
@@ -1676,6 +1690,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {
        .hubp_in_blank = hubp1_in_blank,
        .hubp_soft_reset = hubp1_soft_reset,
        .hubp_set_flip_int = hubp1_set_flip_int,
+       .hubp_clear_tiling = hubp2_clear_tiling,
 };
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
index 18e194507e36ddad3a3106c55a136bc4dd7c663f..7fd9240868c3441fe84b07a031557e8106d88d57 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
@@ -409,6 +409,8 @@ void hubp2_read_state_common(struct hubp *hubp);
 
 void hubp2_read_state(struct hubp *hubp);
 
+void hubp2_clear_tiling(struct hubp *hubp);
+
 #endif /* __DC_MEM_INPUT_DCN20_H__ */
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
index cd2bfcc51276503db21c0b7e5d8567c53b16a2ae..d910e4a54c34abedc9d9431d6951527b0eadaf0b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
@@ -131,6 +131,7 @@ static struct hubp_funcs dcn201_hubp_funcs = {
        .hubp_clear_underflow = hubp1_clear_underflow,
        .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
        .hubp_init = hubp1_init,
+       .hubp_clear_tiling = hubp1_clear_tiling,
 };
 
 bool dcn201_hubp_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
index e13d69a22c1c7fc91fe69696408a46951deb1ceb..edbdb8c88d5c8527d7a2e207cc18a68df714f4a4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
@@ -837,6 +837,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
        .hubp_init = hubp21_init,
        .validate_dml_output = hubp21_validate_dml_output,
        .hubp_set_flip_int = hubp1_set_flip_int,
+       .hubp_clear_tiling = hubp1_clear_tiling,
 };
 
 bool hubp21_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
index 60a64d290352743f2d6ad1148be45d275df89bd0..3b16c3cda2c3e7ab4d13f8a9da2e970ffc9466f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
@@ -334,6 +334,22 @@ void hubp3_program_tiling(
 
 }
 
+void hubp3_clear_tiling(struct hubp *hubp)
+{
+       struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+       REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
+       REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
+
+       REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
+               PRIMARY_SURFACE_DCC_EN, 0,
+               PRIMARY_SURFACE_DCC_IND_BLK, 0,
+               PRIMARY_SURFACE_DCC_IND_BLK_C, 0,
+               SECONDARY_SURFACE_DCC_EN, 0,
+               SECONDARY_SURFACE_DCC_IND_BLK, 0,
+               SECONDARY_SURFACE_DCC_IND_BLK_C, 0);
+}
+
 void hubp3_dcc_control(struct hubp *hubp, bool enable,
                enum hubp_ind_block_size blk_size)
 {
@@ -512,6 +528,7 @@ static struct hubp_funcs dcn30_hubp_funcs = {
        .hubp_in_blank = hubp1_in_blank,
        .hubp_soft_reset = hubp1_soft_reset,
        .hubp_set_flip_int = hubp1_set_flip_int,
+       .hubp_clear_tiling = hubp3_clear_tiling,
 };
 
 bool hubp3_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
index b010531a7fe886cd0c393c70ddfadcd0d40d0b39..cfb01bf340a1a6db449deaa94e3f87bc7b75edf4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
@@ -297,6 +297,8 @@ void hubp3_read_state(struct hubp *hubp);
 
 void hubp3_init(struct hubp *hubp);
 
+void hubp3_clear_tiling(struct hubp *hubp);
+
 #endif /* __DC_HUBP_DCN30_H__ */
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
index 8394e8c069199fd7d63367a0aeaca723899bf99d..46b804ed05fba10399e13eb0eca85a4d92b0cd71 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
@@ -96,6 +96,7 @@ static struct hubp_funcs dcn31_hubp_funcs = {
        .hubp_set_flip_int = hubp1_set_flip_int,
        .hubp_in_blank = hubp1_in_blank,
        .program_extended_blank = hubp31_program_extended_blank,
+       .hubp_clear_tiling = hubp3_clear_tiling,
 };
 
 bool hubp31_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
index ca5b4b28a66441bca370578d11d4e05097db9d4c..8b5bd73b8094a0c37337431b6dcfd513813916bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
@@ -201,7 +201,8 @@ static struct hubp_funcs dcn32_hubp_funcs = {
        .hubp_update_force_cursor_pstate_disallow = hubp32_update_force_cursor_pstate_disallow,
        .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
        .hubp_update_mall_sel = hubp32_update_mall_sel,
-       .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering
+       .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
+       .hubp_clear_tiling = hubp3_clear_tiling,
 };
 
 bool hubp32_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
index d1f05b82b3dd5cb37db23abf994d2e2c6421bc07..eb62042dfafc2d5fcb445ad3c8d0b0a6324fe12b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
@@ -216,6 +216,7 @@ static struct hubp_funcs dcn35_hubp_funcs = {
        .hubp_set_flip_int = hubp1_set_flip_int,
        .hubp_in_blank = hubp1_in_blank,
        .program_extended_blank = hubp31_program_extended_blank_value,
+       .hubp_clear_tiling = hubp3_clear_tiling,
 };
 
 bool hubp35_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 109935be9de85eded4aff227de18faae7c89ef04..09f730cfbf8e2af4b6298a046ff744fb694c4544 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -508,6 +508,18 @@ bool hubp401_program_surface_flip_and_addr(
        return true;
 }
 
+void hubp401_clear_tiling(struct hubp *hubp)
+{
+       struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+       REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
+       REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
+
+       REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+                    PRIMARY_SURFACE_DCC_EN, 0,
+                    SECONDARY_SURFACE_DCC_EN, 0);
+}
+
 void hubp401_dcc_control(struct hubp *hubp,
                struct dc_plane_dcc_param *dcc)
 {
@@ -1004,7 +1016,8 @@ static struct hubp_funcs dcn401_hubp_funcs = {
        .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width,
        .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected,
        .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,
-       .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done
+       .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
+       .hubp_clear_tiling = hubp2_clear_tiling,
 };
 
 bool hubp401_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
index 7d74e63379c6e78e271d614910495e531f43d58f..9b200a55bf9d36b30c9f2ef73c2ec95b67e913ee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
@@ -363,4 +363,6 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma
 
 void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);
 
+void hubp401_clear_tiling(struct hubp *hubp);
+
 #endif /* __DC_HUBP_DCN401_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 16580d62427891fe91001f0e0da8ea301db6b216..d0878fc0cc948b7fcfa1eb6c6d6a3b3ccff467aa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -275,6 +275,7 @@ struct hubp_funcs {
                        enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
                        enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
        int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
+       void (*hubp_clear_tiling)(struct hubp *hubp);
 };
 
 #endif