]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
iommu/io-pgtable-arm: Rationalise MAIR handling
authorRobin Murphy <robin.murphy@arm.com>
Fri, 25 Oct 2019 18:08:36 +0000 (19:08 +0100)
committerWill Deacon <will@kernel.org>
Mon, 4 Nov 2019 19:59:30 +0000 (19:59 +0000)
Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm-smmu-v3.c
drivers/iommu/arm-smmu.c
drivers/iommu/io-pgtable-arm.c
drivers/iommu/ipmmu-vmsa.c
drivers/iommu/qcom_iommu.c
include/linux/io-pgtable.h

index 8da93e730d6fd9f7eb6f1d9a2e8072232c7e3754..3f20e548f1ecad793a7ad01bd16636edf261adb5 100644 (file)
@@ -2172,7 +2172,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
        cfg->cd.asid    = (u16)asid;
        cfg->cd.ttbr    = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
        cfg->cd.tcr     = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
-       cfg->cd.mair    = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
+       cfg->cd.mair    = pgtbl_cfg->arm_lpae_s1_cfg.mair;
        return 0;
 
 out_free_asid:
index a180665ea00275bd5dcc5daee1aab276a759bd49..424ebf38cd09f8d11db8e1a59e8f10f57ca25f6d 100644 (file)
@@ -552,8 +552,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
                        cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;
                        cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;
                } else {
-                       cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
-                       cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
+                       cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair;
+                       cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32;
                }
        }
 }
index fcb30270405377b98c107bb8f3cfda0a1a2483fc..cd96442af44be26a53d914695b5910f3df970fbd 100644 (file)
@@ -861,8 +861,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
              (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
               << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));
 
-       cfg->arm_lpae_s1_cfg.mair[0] = reg;
-       cfg->arm_lpae_s1_cfg.mair[1] = 0;
+       cfg->arm_lpae_s1_cfg.mair = reg;
 
        /* Looking good; allocate a pgd */
        data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),
index 9da8309f71708f213f91dbe99374681e0da3f652..e4da6efbda49cba45154324364fe832a469cbddd 100644 (file)
@@ -438,7 +438,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
 
        /* MAIR0 */
        ipmmu_ctx_write_root(domain, IMMAIR0,
-                            domain->cfg.arm_lpae_s1_cfg.mair[0]);
+                            domain->cfg.arm_lpae_s1_cfg.mair);
 
        /* IMBUSCR */
        if (domain->mmu->features->setup_imbuscr)
index c31e7bc4ccbec2f7083ba30541e2a2b70df7431a..66e9b40e92755aaa2b1c0c222c3b173dac706c00 100644 (file)
@@ -284,9 +284,9 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 
                /* MAIRs (stage-1 only) */
                iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
-                               pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
+                               pgtbl_cfg.arm_lpae_s1_cfg.mair);
                iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
-                               pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);
+                               pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
 
                /* SCTLR */
                reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
index ec7a13405f10bbece1606f51f7f6b27df1dcfe48..ee21eedafe986817ea63f079458b34c593cce933 100644 (file)
@@ -102,7 +102,7 @@ struct io_pgtable_cfg {
                struct {
                        u64     ttbr[2];
                        u64     tcr;
-                       u64     mair[2];
+                       u64     mair;
                } arm_lpae_s1_cfg;
 
                struct {