Merge branch 'pci/controller/dwc'

- Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training more
  robust; this will not affect the intended link width if all lanes are
  functional (Wenbin Yao)

* pci/controller/dwc:
  PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to one lane

diff --cc drivers/pci/controller/dwc/pcie-designware.c
Simple merge