aarch64: fix data cache opcode warning

Wrong logic used in patch.

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index a5c48771782528475bf7baed7494b1bff6c21f99..062c0b3aac8d4679a08a7c120afdfd45cc4cac67 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -8024,10 +8024,10 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
       D5 0B 7E 001 Rt  dc civac, rT
    */
    if (   (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20
-       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
-       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20
-       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7D20
-       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20
+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7D20
+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
       /* Exactly the same scheme as for IC IVAU, except we observe the
          dMinLine size, and request an Ijk_FlushDCache instead of
          Ijk_InvalICache. */