]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amdgpu: Add chain runlists support to GC9.4.2
authorAmber Lin <Amber.Lin@amd.com>
Thu, 17 Jul 2025 15:39:58 +0000 (11:39 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 28 Jul 2025 20:40:32 +0000 (16:40 -0400)
Starting from MEC v97, GC 9.4.2 supports chain runlists of XNACK+/XNACK-
processes.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Philip Yang<Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h

index 20b30f4b3c7d447b57ce0a07b10dae0ab86fd558..6a9cf3587cc6f0a0d00ab1c109fd599dd8aa2579 100644 (file)
@@ -2650,6 +2650,9 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
                                !READ_ONCE(adev->barrier_has_auto_waitcnt));
                WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
                break;
+       case IP_VERSION(9, 4, 2):
+               gfx_v9_4_2_init_sq(adev);
+               break;
        default:
                break;
        }
index c48cd47b531f5a96a01d93f56417e6783934a3aa..8058ea91ecafd84962a8b0c355fc215f5079985c 100644 (file)
@@ -748,6 +748,18 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
        }
 }
 
+void gfx_v9_4_2_init_sq(struct amdgpu_device *adev)
+{
+       uint32_t data;
+
+       if (adev->gfx.mec_fw_version >= 98) {
+               adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN;
+               data = RREG32_SOC15(GC, 0, regSQ_CONFIG1);
+               data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);
+               WREG32_SOC15(GC, 0, regSQ_CONFIG1, data);
+       }
+}
+
 void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
                                uint32_t first_vmid,
                                uint32_t last_vmid)
index 7584624b641cae2bea918f74e8d741a66bf6664a..a603724c1dfc5142bb2af342014556540af47ae3 100644 (file)
@@ -28,6 +28,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
                                uint32_t first_vmid, uint32_t last_vmid);
 void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
                                      uint32_t die_id);
+void gfx_v9_4_2_init_sq(struct amdgpu_device *adev);
 void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);
 int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev);