iio: dac: ad3552r-hs: use instruction mode for configuration

Use "instruction" mode over initial configuration and all other
non-streaming operations.

DAC boots in streaming mode as default, and the driver is not
changing this mode.

Instruction r/w is still working because instruction is processed
from the DAC after chip select is deasserted, this works until
loop mode is 0 or greater than the instruction size.

All initial operations should be more safely done in instruction
mode, a mode provided for this.

Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250114-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v4-6-979402e33545@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c
index 6bf995b503958eb53bd756d0722a717706cec04d..25ee716b57cd33a656277bbf03e768b51dda296f 100644 (file)
--- a/drivers/iio/dac/ad3552r-hs.c
+++ b/drivers/iio/dac/ad3552r-hs.c
@@ -137,13 +137,20 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
        if (ret)
                return ret;
 
+       /* Primary region access, set streaming mode (now in SPI + SDR). */
+       ret = ad3552r_qspi_update_reg_bits(st,
+                                          AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+                                          AD3552R_MASK_SINGLE_INST, 0, 1);
+       if (ret)
+               return ret;
+
        /* Inform DAC chip to switch into DDR mode */
        ret = ad3552r_qspi_update_reg_bits(st,
                                           AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
                                           AD3552R_MASK_SPI_CONFIG_DDR,
                                           AD3552R_MASK_SPI_CONFIG_DDR, 1);
        if (ret)
-               return ret;
+               goto exit_err_ddr;
 
        /* Inform DAC IP to go for DDR mode from now on */
        ret = iio_backend_ddr_enable(st->back);
@@ -174,6 +181,11 @@ exit_err:
 
        iio_backend_ddr_disable(st->back);
 
+exit_err_ddr:
+       ad3552r_qspi_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+                                    AD3552R_MASK_SINGLE_INST,
+                                    AD3552R_MASK_SINGLE_INST, 1);
+
        return ret;
 }
 
@@ -198,6 +210,14 @@ static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev)
        if (ret)
                return ret;
 
+       /* Back to single instruction mode, disabling loop. */
+       ret = ad3552r_qspi_update_reg_bits(st,
+                                          AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+                                          AD3552R_MASK_SINGLE_INST,
+                                          AD3552R_MASK_SINGLE_INST, 1);
+       if (ret)
+               return ret;
+
        return 0;
 }
 
@@ -308,6 +328,13 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *st)
        if (ret)
                return ret;
 
+       ret = st->data->bus_reg_write(st->back,
+                                     AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+                                     AD3552R_MASK_SINGLE_INST |
+                                     AD3552R_MASK_SHORT_INSTRUCTION, 1);
+       if (ret)
+               return ret;
+
        ret = ad3552r_hs_scratch_pad_test(st);
        if (ret)
                return ret;