tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'

To avoid including the huge "cpu.h" for a simple definition,
move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
index 50c18bd326d1e6e93c8192e2f4c558d8714eb9ec..c439c09f2feb61ea7bf5a7d02e904b7f8f2797cc 100644 (file)
--- a/include/tcg/insn-start-words.h
+++ b/include/tcg/insn-start-words.h
@@ -6,7 +6,7 @@
 
 #ifndef TARGET_INSN_START_WORDS
 
-#include "cpu.h"
+#include "cpu-param.h"
 
 #ifndef TARGET_INSN_START_EXTRA_WORDS
 # define TARGET_INSN_START_WORDS 1

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index a7ae42d17dca346375b112d145e28f149ed5ee76..2cee4be693869d7369be53eed689b89731bf4723 100644 (file)
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -37,6 +37,13 @@
 # define TARGET_PAGE_BITS_LEGACY 10
 #endif /* !CONFIG_USER_ONLY */
 
+/*
+ * ARM-specific extra insn start words:
+ * 1: Conditional execution bits
+ * 2: Partial exception syndrome for data aborts
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /* ARM processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c1a0faed3ad271ab0c2a8c716f4eb7de8983575f..3705b34285b2c84a0027b4ac3f75b84f03593370 100644 (file)
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -98,12 +98,6 @@
 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
 #endif
 
-/* ARM-specific extra insn start words:
- * 1: Conditional execution bits
- * 2: Partial exception syndrome for data aborts
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 /* The 2nd extra word holding syndrome info for data aborts does not use
  * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
  * help the sleb128 encoder do a better job.

diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 7ed6b5741e7b1b56f73cba98da9d01fde3dca8c2..68ed84e84af710925df449e388b556809ac71b28 100644 (file)
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -19,6 +19,8 @@
 
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /* PA-RISC 1.x processors have a strong memory model.  */
 /*
  * ??? While we do not yet implement PA-RISC 2.0, those processors have

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index da5f8adcd5890c55bdb21ccdf82696922ceee3c3..acc9937240485d05386c5fcde78395d0757d732c 100644 (file)
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -48,8 +48,6 @@
 #define PRIV_KERNEL       0
 #define PRIV_USER         3
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 /* No need to flush MMU_ABS*_IDX  */
 #define HPPA_MMU_FLUSH_MASK                             \
         (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX |  \

diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index b0e884c5d704ab0197f1dd1d9db20bce029ac972..0c8efce8619860d6dc8a439e08ad0dcd86fdc7c7 100644 (file)
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,8 @@
 #endif
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /* The x86 has a strong memory model with some store-after-load re-ordering */
 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
 

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 17ad0b644bd97bafc630d9e4bee24ec488a7f200..9866595cd0e50d371f6440b621590f3655ed8d57 100644 (file)
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1610,8 +1610,6 @@ typedef struct {
 #define MAX_FIXED_COUNTERS 3
 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 #define NB_OPMASK_REGS 8
 
 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish

diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 7afbf6d302dd2708ce5ffdda93a395128ed9a706..256a2b5f8b298b92d258a2a3f184430f545db537 100644 (file)
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,4 +17,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #endif

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 0b70e8c6ab644cc76ac746feaf74831e114ad2f9..39d0b9d6d73e3a2b11381b6911d216a7996ff3c8 100644 (file)
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -78,8 +78,6 @@
 #define M68K_MAX_TTR 2
 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 typedef CPU_LDoubleU FPReg;
 
 typedef struct CPUArchState {

diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index c866ec6c1495e80d88d0417561fb5f954982968b..5d55e0e3c4afe578d4888e5f1650ab76bc0f1520 100644 (file)
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -27,6 +27,8 @@
 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /* MicroBlaze is always in-order. */
 #define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL
 

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 2bfa396c96d765c99b23366f95cfcf2fcead16c2..d511f22a559201dbe977d778db215ef9f8f63d41 100644 (file)
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -233,8 +233,6 @@ typedef struct CPUArchState CPUMBState;
 #define STREAM_CONTROL   (1 << 3)
 #define STREAM_NONBLOCK  (1 << 4)
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 /* use-non-secure property masks */
 #define USE_NON_SECURE_M_AXI_DP_MASK 0x1
 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2

diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 8fcb1b4f5f2c79b585b42570fc758716b9c00809..99ca8d1684c52d6c815d0f4a88b76cc0ac324c37 100644 (file)
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -20,6 +20,8 @@
 #endif
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 20f31370bcbfaafc2931744ef1456c1a19095550..d16f9a7220e19ff5dcfa2c87a0022aee384fdaff 100644 (file)
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -100,8 +100,6 @@ struct CPUMIPSFPUContext {
 #define FP_UNIMPLEMENTED  32
 };
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 struct CPUMIPSMVPContext {
     int32_t CP0_MVPControl;

diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 37627f2c394ffaac4c333e248abb3f585c14be0c..7ea0ecb55a6046ce5f88ca31c5759a9cc9b492ac 100644 (file)
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -12,6 +12,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 19ee85ff5a07bf5a38ee40a1917543b925abe22b..569819bfb0b2453f91a712e710696629c368eaa8 100644 (file)
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -40,8 +40,6 @@ struct OpenRISCCPUClass {
     ResettablePhases parent_phases;
 };
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 enum {
     MMU_NOMMU_IDX = 0,
     MMU_SUPERVISOR_IDX = 1,

diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index fba30e966a824742eedeb0c03de6356d3a11d246..ff4ba81965acba352fe81c9788d2674771b48495 100644 (file)
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,14 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
 #endif
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+
+/*
+ * RISC-V-specific extra insn start words:
+ * 1: Original instruction opcode
+ * 2: more information about instruction
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /*
  * The current MMU Modes are:
  *  - U mode 0b000

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 867e539b53a75b1d43dd35d18e7f209ba4f8fa4a..167909c89bc1adc0b6f63eddef3e6ba565142306 100644 (file)
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -45,12 +45,6 @@ typedef struct CPUArchState CPURISCVState;
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif
 
-/*
- * RISC-V-specific extra insn start words:
- * 1: Original instruction opcode
- * 2: more information about instruction
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
 /*
  * b0: Whether a instruction always raise a store AMO or not.
  */

diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 5c331ec424c11cce92ca83d418dc6c67d8a9429d..a8a4377f4ffd06346c0a2e20e46885b7736e0bc9 100644 (file)
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -12,6 +12,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 64
 #define TARGET_VIRT_ADDR_SPACE_BITS 64
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /*
  * The z/Architecture has a strong memory model with some
  * store-after-load re-ordering.

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 940eda8dd12374b0c08c37fce72ef60583e2073b..90f64ee20cc750bea30b376e39ba934a7c9ecadc 100644 (file)
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -37,8 +37,6 @@
 
 #define TARGET_HAS_PRECISE_SMC
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 #define MMU_USER_IDX 0
 
 #define S390_MAX_CPUS 248

diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 2b6e11dd0acab6dcf549fed157775ca2d9ca9806..f328715ee862f9e99663286e006ca23295f01d9d 100644 (file)
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,4 +16,6 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #endif

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 7752a0c2e1a509ee04c47a4e7ad93f9eb1f2d248..906f99ddf0065b8b047d8d84afb059b1e89c89b6 100644 (file)
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -127,8 +127,6 @@ typedef struct tlb_t {
 #define UTLB_SIZE 64
 #define ITLB_SIZE 4
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 enum sh_features {
     SH_FEATURE_SH4A = 1,
     SH_FEATURE_BCR3_AND_BCR4 = 2,

diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 6952ee2b82663705961a1c2bca92f916ef81d0e9..62d47b804bb354cf985a56489d702119de1f41d5 100644 (file)
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -21,6 +21,8 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /*
  * From Oracle SPARC Architecture 2015:
  *

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 734dfdb1d3d3aa8537ce3194befb3dd4bf678120..83ac818933bfb873ad2b391fe29a257d5387ea57 100644 (file)
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -223,7 +223,6 @@ typedef struct trap_state {
     uint32_t tt;
 } trap_state;
 #endif
-#define TARGET_INSN_START_EXTRA_WORDS 1
 
 typedef struct sparc_def_t {
     const char *name;