RISC-V: Add vzext.vf8 C++ API tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vzext_vf8-1.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8-2.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8-3.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C: New test.

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C
new file mode 100644 (file)
index 0000000..caf23bc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C
new file mode 100644 (file)
index 0000000..b021b28
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C
new file mode 100644 (file)
index 0000000..8904ac4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C
new file mode 100644 (file)
index 0000000..5d96491
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C
new file mode 100644 (file)
index 0000000..c4d24b8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C
new file mode 100644 (file)
index 0000000..74bd3ca
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C
new file mode 100644 (file)
index 0000000..f782835
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C
new file mode 100644 (file)
index 0000000..9ca4012
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C
new file mode 100644 (file)
index 0000000..5b8c5e4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C
new file mode 100644 (file)
index 0000000..b7538f1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C
new file mode 100644 (file)
index 0000000..10869ac
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C
new file mode 100644 (file)
index 0000000..e67a477
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C
new file mode 100644 (file)
index 0000000..78d14a4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C
new file mode 100644 (file)
index 0000000..900920f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C
new file mode 100644 (file)
index 0000000..f8efb69
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf8_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */