ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism

v1 was the incorrect choice here and sometimes the board
would not come up properly.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 78db67337ed4a3ce90a8962f183444296c27fc53..bbb230b743b2b823716e53ab87103c91c50f899d 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -52,7 +52,8 @@
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
                        qcom,saw = <&saw0>;
                        reg = <0x0>;
@@ -71,7 +72,8 @@
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
                        qcom,saw = <&saw1>;
                        reg = <0x1>;
@@ -90,7 +92,8 @@
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
                        qcom,saw = <&saw2>;
                        reg = <0x2>;
@@ -109,7 +112,8 @@
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       enable-method = "qcom,kpss-acc-v1";
+                       enable-method = "qcom,kpss-acc-v2";
+                       next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
                        qcom,saw = <&saw3>;
                        reg = <0x3>;
@@ -124,6 +128,11 @@
                        >;
                        clock-latency = <256000>;
                };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+               };
        };
 
        pmu {
@@ -292,22 +301,22 @@
                };
 
                 acc0: clock-controller@b088000 {
-                        compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v2";
                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
                 };
 
                 acc1: clock-controller@b098000 {
-                        compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v2";
                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
                 };
 
                 acc2: clock-controller@b0a8000 {
-                        compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v2";
                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
                 };
 
                 acc3: clock-controller@b0b8000 {
-                        compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v2";
                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
                 };