--- /dev/null
+From b4f15f808b9a79b6ad9032fa5f6d8b88e1e1bf11 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 25 Oct 2011 11:34:51 -0400
+Subject: drm/radeon/kms: cleanup atombios_adjust_pll()
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit b4f15f808b9a79b6ad9032fa5f6d8b88e1e1bf11 upstream.
+
+The logic was messy and hard to follow.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 41 ++++++++++-----------------------
+ 1 file changed, 13 insertions(+), 28 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -638,38 +638,23 @@ static u32 atombios_adjust_pll(struct dr
+ if (ss_enabled && ss->percentage)
+ args.v3.sInput.ucDispPllConfig |=
+ DISPPLL_CONFIG_SS_ENABLE;
+- if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
+- radeon_encoder_is_dp_bridge(encoder)) {
++ if (encoder_mode == ATOM_ENCODER_MODE_DP) {
++ args.v3.sInput.ucDispPllConfig |=
++ DISPPLL_CONFIG_COHERENT_MODE;
++ /* 16200 or 27000 */
++ args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
++ } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+- if (encoder_mode == ATOM_ENCODER_MODE_DP) {
++ if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
++ /* deep color support */
++ args.v3.sInput.usPixelClock =
++ cpu_to_le16((mode->clock * bpc / 8) / 10);
++ if (dig->coherent_mode)
+ args.v3.sInput.ucDispPllConfig |=
+ DISPPLL_CONFIG_COHERENT_MODE;
+- /* 16200 or 27000 */
+- args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
+- } else {
+- if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
+- /* deep color support */
+- args.v3.sInput.usPixelClock =
+- cpu_to_le16((mode->clock * bpc / 8) / 10);
+- }
+- if (dig->coherent_mode)
+- args.v3.sInput.ucDispPllConfig |=
+- DISPPLL_CONFIG_COHERENT_MODE;
+- if (mode->clock > 165000)
+- args.v3.sInput.ucDispPllConfig |=
+- DISPPLL_CONFIG_DUAL_LINK;
+- }
+- } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+- if (encoder_mode == ATOM_ENCODER_MODE_DP) {
++ if (mode->clock > 165000)
+ args.v3.sInput.ucDispPllConfig |=
+- DISPPLL_CONFIG_COHERENT_MODE;
+- /* 16200 or 27000 */
+- args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
+- } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
+- if (mode->clock > 165000)
+- args.v3.sInput.ucDispPllConfig |=
+- DISPPLL_CONFIG_DUAL_LINK;
+- }
++ DISPPLL_CONFIG_DUAL_LINK;
+ }
+ if (radeon_encoder_is_dp_bridge(encoder)) {
+ struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
--- /dev/null
+From 1d33e1fc8dcce667a70387b666a8b6f60153d90f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 31 Oct 2011 08:58:47 -0400
+Subject: drm/radeon/kms: rework DP bridge checks
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 1d33e1fc8dcce667a70387b666a8b6f60153d90f upstream.
+
+Return the encoder id rather than a boolean. This is needed
+for differentiate between multiple DP bridge chips.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 12 ++++++------
+ drivers/gpu/drm/radeon/atombios_dp.c | 6 ++++--
+ drivers/gpu/drm/radeon/radeon_connectors.c | 16 +++++++---------
+ drivers/gpu/drm/radeon/radeon_display.c | 3 ++-
+ drivers/gpu/drm/radeon/radeon_encoders.c | 11 ++++++-----
+ drivers/gpu/drm/radeon/radeon_mode.h | 4 ++--
+ 6 files changed, 27 insertions(+), 25 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -558,7 +558,7 @@ static u32 atombios_adjust_pll(struct dr
+ bpc = connector->display_info.bpc;
+ encoder_mode = atombios_get_encoder_mode(encoder);
+ if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
+- radeon_encoder_is_dp_bridge(encoder)) {
++ (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
+ if (connector) {
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+ struct radeon_connector_atom_dig *dig_connector =
+@@ -656,11 +656,11 @@ static u32 atombios_adjust_pll(struct dr
+ args.v3.sInput.ucDispPllConfig |=
+ DISPPLL_CONFIG_DUAL_LINK;
+ }
+- if (radeon_encoder_is_dp_bridge(encoder)) {
+- struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
+- struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
+- args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
+- } else
++ if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
++ ENCODER_OBJECT_ID_NONE)
++ args.v3.sInput.ucExtTransmitterID =
++ radeon_encoder_get_dp_bridge_encoder_id(encoder);
++ else
+ args.v3.sInput.ucExtTransmitterID = 0;
+
+ atom_execute_table(rdev->mode_info.atom_context,
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -482,7 +482,8 @@ static int radeon_dp_get_dp_link_clock(s
+ int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
+ int lane_num, max_pix_clock;
+
+- if (radeon_connector_encoder_is_dp_bridge(connector))
++ if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++ ENCODER_OBJECT_ID_NONE)
+ return 270000;
+
+ lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
+@@ -559,7 +560,8 @@ static void radeon_dp_set_panel_mode(str
+ if (!ASIC_IS_DCE4(rdev))
+ return;
+
+- if (radeon_connector_encoder_is_dp_bridge(connector))
++ if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++ ENCODER_OBJECT_ID_NONE)
+ panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+ else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -44,8 +44,6 @@ extern void
+ radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
+ struct drm_connector *drm_connector);
+
+-bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
+-
+ void radeon_connector_hotplug(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+@@ -1204,7 +1202,8 @@ static int radeon_dp_get_modes(struct dr
+ }
+ } else {
+ /* need to setup ddc on the bridge */
+- if (radeon_connector_encoder_is_dp_bridge(connector)) {
++ if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++ ENCODER_OBJECT_ID_NONE) {
+ if (encoder)
+ radeon_atom_ext_encoder_setup_ddc(encoder);
+ }
+@@ -1214,13 +1213,12 @@ static int radeon_dp_get_modes(struct dr
+ return ret;
+ }
+
+-bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector)
++u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
+ {
+ struct drm_mode_object *obj;
+ struct drm_encoder *encoder;
+ struct radeon_encoder *radeon_encoder;
+ int i;
+- bool found = false;
+
+ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ if (connector->encoder_ids[i] == 0)
+@@ -1236,14 +1234,13 @@ bool radeon_connector_encoder_is_dp_brid
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_TRAVIS:
+ case ENCODER_OBJECT_ID_NUTMEG:
+- found = true;
+- break;
++ return radeon_encoder->encoder_id;
+ default:
+ break;
+ }
+ }
+
+- return found;
++ return ENCODER_OBJECT_ID_NONE;
+ }
+
+ bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
+@@ -1320,7 +1317,8 @@ radeon_dp_detect(struct drm_connector *c
+ if (!radeon_dig_connector->edp_on)
+ atombios_set_edp_panel_power(connector,
+ ATOM_TRANSMITTER_ACTION_POWER_OFF);
+- } else if (radeon_connector_encoder_is_dp_bridge(connector)) {
++ } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++ ENCODER_OBJECT_ID_NONE) {
+ /* DP bridges are always DP */
+ radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
+ /* get the DPCD from the bridge */
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -708,7 +708,8 @@ int radeon_ddc_get_modes(struct radeon_c
+
+ if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+ (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
+- radeon_connector_encoder_is_dp_bridge(&radeon_connector->base)) {
++ (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
++ ENCODER_OBJECT_ID_NONE)) {
+ struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
+
+ if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
+--- a/drivers/gpu/drm/radeon/radeon_encoders.c
++++ b/drivers/gpu/drm/radeon/radeon_encoders.c
+@@ -266,7 +266,7 @@ struct drm_encoder *radeon_atom_get_exte
+ return NULL;
+ }
+
+-bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
++u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
+ {
+ struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
+
+@@ -368,7 +368,7 @@ static bool radeon_atom_mode_fixup(struc
+
+ if (ASIC_IS_DCE3(rdev) &&
+ ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
+- radeon_encoder_is_dp_bridge(encoder))) {
++ (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
+ struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+ radeon_dp_set_link_config(connector, mode);
+ }
+@@ -658,7 +658,7 @@ atombios_get_encoder_mode(struct drm_enc
+ struct radeon_connector_atom_dig *dig_connector;
+
+ /* dp bridges are always DP */
+- if (radeon_encoder_is_dp_bridge(encoder))
++ if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
+ return ATOM_ENCODER_MODE_DP;
+
+ /* DVO is always DVO */
+@@ -1638,7 +1638,7 @@ atombios_set_encoder_crtc_source(struct
+ break;
+ case 2:
+ args.v2.ucCRTC = radeon_crtc->crtc_id;
+- if (radeon_encoder_is_dp_bridge(encoder)) {
++ if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
+ struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+
+ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
+@@ -2099,7 +2099,8 @@ static void radeon_atom_encoder_prepare(
+
+ if ((radeon_encoder->active_device &
+ (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
+- radeon_encoder_is_dp_bridge(encoder)) {
++ (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
++ ENCODER_OBJECT_ID_NONE)) {
+ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+ if (dig)
+ dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
+--- a/drivers/gpu/drm/radeon/radeon_mode.h
++++ b/drivers/gpu/drm/radeon/radeon_mode.h
+@@ -468,8 +468,8 @@ radeon_atombios_get_tv_info(struct radeo
+ extern struct drm_connector *
+ radeon_get_connector_for_encoder(struct drm_encoder *encoder);
+
+-extern bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder);
+-extern bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
++extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
++extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
+ extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
+ extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
