drm/i915/dmc: Drop PIPEDMC faults from the fault mask on LNL+

On LNL+ PIPEDMC faults are reported via PIPEDMC interrupts
instead of the direct DE_PIPE_* reporting used on earlier
platforms. Drop the relevant bits from the fault mask.

The bits are tied to zero on LNL, so there is no danger of
spurious fault interrupts even with an incorrect mask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-2-ville.syrjala@linux.intel.com
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 3e73832e5e8132447fd5a5719dce4d489a547afe..a7130b14aaceeecd6969b0979be36c6583e6a6fc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1016,7 +1016,15 @@ static u32 gen8_de_port_aux_mask(struct intel_display *display)
 
 static u32 gen8_de_pipe_fault_mask(struct intel_display *display)
 {
-       if (DISPLAY_VER(display) >= 14)
+       if (DISPLAY_VER(display) >= 20)
+               return MTL_PLANE_ATS_FAULT |
+                       GEN9_PIPE_CURSOR_FAULT |
+                       GEN11_PIPE_PLANE5_FAULT |
+                       GEN9_PIPE_PLANE4_FAULT |
+                       GEN9_PIPE_PLANE3_FAULT |
+                       GEN9_PIPE_PLANE2_FAULT |
+                       GEN9_PIPE_PLANE1_FAULT;
+       else if (DISPLAY_VER(display) >= 14)
                return MTL_PIPEDMC_ATS_FAULT |
                        MTL_PLANE_ATS_FAULT |
                        GEN12_PIPEDMC_FAULT |

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e4190da3e0d8b62a1a952bf0ac19afa3c4081d1..2d0e04eae7630a16fe28f4591f77dabd5f5c3743 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2126,8 +2126,8 @@
 #define  GEN8_PIPE_CDCLK_CRC_ERROR     REG_BIT(29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE      REG_BIT(28)
 #define  GEN12_PIPEDMC_INTERRUPT       REG_BIT(26) /* tgl+ */
-#define  GEN12_PIPEDMC_FAULT           REG_BIT(25) /* tgl+ */
-#define  MTL_PIPEDMC_ATS_FAULT         REG_BIT(24) /* mtl+ */
+#define  GEN12_PIPEDMC_FAULT           REG_BIT(25) /* tgl-mtl */
+#define  MTL_PIPEDMC_ATS_FAULT         REG_BIT(24) /* mtl */
 #define  GEN11_PIPE_PLANE7_FAULT       REG_BIT(22) /* icl/tgl */
 #define  GEN11_PIPE_PLANE6_FAULT       REG_BIT(21) /* icl/tgl */
 #define  GEN11_PIPE_PLANE5_FAULT       REG_BIT(20) /* icl+ */