arm64 front end: mark a couple of vector load/store insns as "verbose".

Mark
   LD3/ST3 (multiple 3-elem structs to/from 3 regs
   LD4/ST4 (multiple 4-elem structs to/from 4 regs
as "verbose", since they can generate so much IR that a long sequence
of them causes later stages of the JIT to run out of space.

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index fa4596a905f7f18e436773bdf4fdb902aed6782a..556b85a6aff77878f4b5db46518e793a68924d2f 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -6040,6 +6040,9 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
              (tt+0) % 32, arr, (tt+nRegs-1) % 32, arr, nameIReg64orSP(nn),
              pxStr);
 
+         if (nRegs >= 3) {
+            dres->hint = Dis_HintVerbose;
+         }
          return True;
       }
       /* else fall through */