--- /dev/null
+From cb8cc37f4d38d96552f2c52deb15e511cdacf906 Mon Sep 17 00:00:00 2001
+From: Caesar Wang <wxt@rock-chips.com>
+Date: Mon, 6 Jul 2015 11:37:23 +0800
+Subject: ARM: rockchip: fix broken build
+
+From: Caesar Wang <wxt@rock-chips.com>
+
+commit cb8cc37f4d38d96552f2c52deb15e511cdacf906 upstream.
+
+The following was seen in branch[0] build.
+
+arch/arm/mach-rockchip/platsmp.c:154:23: error:
+ 'rockchip_secondary_startup' undeclared (first use in this function)
+
+branch[0]:
+git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
+v4.3-armsoc/soc
+
+The broken build is caused by the commit fe4407c0dc58
+("ARM: rockchip: fix the CPU soft reset").
+
+Signed-off-by: Caesar Wang <wxt@rock-chips.com>
+
+The breakage was a result of it being wrongly merged in my branch with
+the cache invalidation rework from Russell 02b4e2756e01c
+("ARM: v7 setup function should invalidate L1 cache").
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Cc: Willy Tarreau <w@1wt.eu>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-rockchip/platsmp.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/arch/arm/mach-rockchip/platsmp.c
++++ b/arch/arm/mach-rockchip/platsmp.c
+@@ -152,8 +152,7 @@ static int __cpuinit rockchip_boot_secon
+ * */
+ mdelay(1); /* ensure the cpus other than cpu0 to startup */
+
+- writel(virt_to_phys(rockchip_secondary_startup),
+- sram_base_addr + 8);
++ writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
+ writel(0xDEADBEAF, sram_base_addr + 4);
+ dsb_sev();
+ }