3.18-stable patches

added patches:
	x86-microcode-intel-extend-bdw-late-loading-further-with-llc-size-check.patch

diff --git a/queue-3.18/series b/queue-3.18/series
index d4da0ee88f3093648e4150938e2965f42eb7d65c..8c9b3ec3b20ea7b650f7a52a3890f465bbf585eb 100644 (file)
--- a/queue-3.18/series
+++ b/queue-3.18/series
@@ -37,3 +37,4 @@ um-link-vmlinux-with-no-pie.patch
 eventpoll.h-add-missing-epoll-event-masks.patch
 um-stop-abusing-__kernel__.patch
 um-remove-copy-paste-code-from-init.h.patch
+x86-microcode-intel-extend-bdw-late-loading-further-with-llc-size-check.patch

diff --git a/queue-3.18/x86-microcode-intel-extend-bdw-late-loading-further-with-llc-size-check.patch b/queue-3.18/x86-microcode-intel-extend-bdw-late-loading-further-with-llc-size-check.patch
new file mode 100644 (file)
index 0000000..42e5fa0
--- /dev/null
+++ b/queue-3.18/x86-microcode-intel-extend-bdw-late-loading-further-with-llc-size-check.patch
@@ -0,0 +1,90 @@
+From 7e702d17ed138cf4ae7c00e8c00681ed464587c7 Mon Sep 17 00:00:00 2001
+From: Jia Zhang <zhang.jia@linux.alibaba.com>
+Date: Tue, 23 Jan 2018 11:41:32 +0100
+Subject: x86/microcode/intel: Extend BDW late-loading further with LLC size check
+
+From: Jia Zhang <zhang.jia@linux.alibaba.com>
+
+commit 7e702d17ed138cf4ae7c00e8c00681ed464587c7 upstream.
+
+Commit b94b73733171 ("x86/microcode/intel: Extend BDW late-loading with a
+revision check") reduced the impact of erratum BDF90 for Broadwell model
+79.
+
+The impact can be reduced further by checking the size of the last level
+cache portion per core.
+
+Tony: "The erratum says the problem only occurs on the large-cache SKUs.
+So we only need to avoid the update if we are on a big cache SKU that is
+also running old microcode."
+
+For more details, see erratum BDF90 in document #334165 (Intel Xeon
+Processor E7-8800/4800 v4 Product Family Specification Update) from
+September 2017.
+
+Fixes: b94b73733171 ("x86/microcode/intel: Extend BDW late-loading with a revision check")
+Signed-off-by: Jia Zhang <zhang.jia@linux.alibaba.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Tony Luck <tony.luck@intel.com>
+Link: https://lkml.kernel.org/r/1516321542-31161-1-git-send-email-zhang.jia@linux.alibaba.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/cpu/microcode/intel.c |   20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/microcode/intel.c
++++ b/arch/x86/kernel/cpu/microcode/intel.c
+@@ -87,6 +87,9 @@ MODULE_DESCRIPTION("Microcode Update Dri
+ MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
+ MODULE_LICENSE("GPL");
+ 
++/* last level cache size per core */
++static int llc_size_per_core;
++
+ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
+ {
+       struct cpuinfo_x86 *c = &cpu_data(cpu_num);
+@@ -273,12 +276,14 @@ static bool is_blacklisted(unsigned int
+ 
+       /*
+        * Late loading on model 79 with microcode revision less than 0x0b000021
+-       * may result in a system hang. This behavior is documented in item
+-       * BDF90, #334165 (Intel Xeon Processor E7-8800/4800 v4 Product Family).
++       * and LLC size per core bigger than 2.5MB may result in a system hang.
++       * This behavior is documented in item BDF90, #334165 (Intel Xeon
++       * Processor E7-8800/4800 v4 Product Family).
+        */
+       if (c->x86 == 6 &&
+           c->x86_model == 79 &&
+           c->x86_mask == 0x01 &&
++          llc_size_per_core > 2621440 &&
+           c->microcode < 0x0b000021) {
+               pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
+               pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
+@@ -345,6 +350,15 @@ static struct microcode_ops microcode_in
+       .microcode_fini_cpu               = microcode_fini_cpu,
+ };
+ 
++static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
++{
++      u64 llc_size = c->x86_cache_size * 1024;
++
++      do_div(llc_size, c->x86_max_cores);
++
++      return (int)llc_size;
++}
++
+ struct microcode_ops * __init init_intel_microcode(void)
+ {
+       struct cpuinfo_x86 *c = &cpu_data(0);
+@@ -355,6 +369,8 @@ struct microcode_ops * __init init_intel
+               return NULL;
+       }
+ 
++      llc_size_per_core = calc_llc_size_per_core(c);
++
+       return &microcode_intel_ops;
+ }
+