x86/APX: be consistent with insn suffixes

When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.

diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd.d b/gas/testsuite/gas/i386/x86-64-apx-ndd.d
index 36d5c738e461aae917c5011711e6e37061ca5152..e08a2ddd37ef205209f209db3d8fab7a86f74fa6 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-apx-ndd.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
 \s*[a-f0-9]+:\s*62 54 6c 10 11 38      adc    %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 12 04 07   adc    \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 13 04 07   adc    \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 14 83 11        adcl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 14 83 11        adc    \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*62 54 6d 10 66 c7      adcx   %r15d,%r8d,%r18d
 \s*[a-f0-9]+:\s*62 14 f9 08 66 04 3f   adcx   \(%r15,%r31,1\),%r8
 \s*[a-f0-9]+:\s*62 14 69 10 66 04 3f   adcx   \(%r15,%r31,1\),%r8d,%r18d
@@ -32,9 +32,9 @@ Disassembly of section .text:
 \s*[a-f0-9]+:\s*62 5c f8 10 03 84 07 90 90 00 00       add    0x9090\(%r31,%r16,1\),%r8,%r16
 \s*[a-f0-9]+:\s*62 44 7c 10 00 f8      add    %r31b,%r8b,%r16b
 \s*[a-f0-9]+:\s*62 44 7c 10 01 f8      add    %r31d,%r8d,%r16d
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 04 83 11        addl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 04 83 11        add    \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*62 44 fc 10 01 f8      add    %r31,%r8,%r16
-\s*[a-f0-9]+:\s*62 d4 fc 10 81 04 8f 33 44 34 12       addq   \$0x12344433,\(%r15,%rcx,4\),%r16
+\s*[a-f0-9]+:\s*62 d4 fc 10 81 04 8f 33 44 34 12       add    \$0x12344433,\(%r15,%rcx,4\),%r16
 \s*[a-f0-9]+:\s*62 44 7d 10 01 f8      add    %r31w,%r8w,%r16w
 \s*[a-f0-9]+:\s*62 54 6e 10 66 c7      adox   %r15d,%r8d,%r18d
 \s*[a-f0-9]+:\s*62 5c fc 10 03 c7      add    %r31,%r8,%r16
@@ -46,7 +46,7 @@ Disassembly of section .text:
 \s*[a-f0-9]+:\s*62 54 6c 10 21 38      and    %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 22 04 07   and    \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 23 04 07   and    \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 24 83 11        andl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 24 83 11        and    \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 47 90 90 90 90 90       cmova  -0x6f6f6f70\(%eax\),%edx,%r8d
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 43 90 90 90 90 90       cmovae -0x6f6f6f70\(%eax\),%edx,%r8d
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 42 90 90 90 90 90       cmovb  -0x6f6f6f70\(%eax\),%edx,%r8d
@@ -64,98 +64,98 @@ Disassembly of section .text:
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 4a 90 90 90 90 90       cmovp  -0x6f6f6f70\(%eax\),%edx,%r8d
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 48 90 90 90 90 90       cmovs  -0x6f6f6f70\(%eax\),%edx,%r8d
 \s*[a-f0-9]+:\s*62 f4 f4 10 ff c8      dec    %rax,%r17
-\s*[a-f0-9]+:\s*62 9c 3c 18 fe 0c 27   decb   \(%r31,%r12,1\),%r8b
+\s*[a-f0-9]+:\s*62 9c 3c 18 fe 0c 27   dec    \(%r31,%r12,1\),%r8b
 \s*[a-f0-9]+:\s*62 b4 b0 10 af 94 f8 09 09 00 00       imul   0x909\(%rax,%r31,8\),%rdx,%r25
 \s*[a-f0-9]+:\s*67 62 f4 3c 18 af 90 09 09 09 00       imul   0x90909\(%eax\),%edx,%r8d
 \s*[a-f0-9]+:\s*62 dc fc 10 ff c7      inc    %r31,%r16
 \s*[a-f0-9]+:\s*62 dc bc 18 ff c7      inc    %r31,%r8
 \s*[a-f0-9]+:\s*62 f4 e4 18 ff c0      inc    %rax,%rbx
 \s*[a-f0-9]+:\s*62 f4 f4 10 f7 d8      neg    %rax,%r17
-\s*[a-f0-9]+:\s*62 9c 3c 18 f6 1c 27   negb   \(%r31,%r12,1\),%r8b
+\s*[a-f0-9]+:\s*62 9c 3c 18 f6 1c 27   neg    \(%r31,%r12,1\),%r8b
 \s*[a-f0-9]+:\s*62 f4 f4 10 f7 d0      not    %rax,%r17
-\s*[a-f0-9]+:\s*62 9c 3c 18 f6 14 27   notb   \(%r31,%r12,1\),%r8b
+\s*[a-f0-9]+:\s*62 9c 3c 18 f6 14 27   not    \(%r31,%r12,1\),%r8b
 \s*[a-f0-9]+:\s*62 f4 0d 10 81 c8 34 12        or     \$0x1234,%ax,%r30w
 \s*[a-f0-9]+:\s*62 7c 6c 10 08 f9      or     %r15b,%r17b,%r18b
 \s*[a-f0-9]+:\s*62 54 6c 10 09 38      or     %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 0a 04 07   or     \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 0b 04 07   or     \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 0c 83 11        orl    \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 0c 83 11        or     \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 d4 02   rcl    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 d0      rcl    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 10      rclb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 10 02   rcll   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 10      rclw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 14 83   rclw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 10      rcl    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 10 02   rcl    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 10      rcl    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 14 83   rcl    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 dc 02   rcr    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 d8      rcr    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 18      rcrb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 18 02   rcrl   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 18      rcrw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 1c 83   rcrw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 18      rcr    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 18 02   rcr    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 18      rcr    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 1c 83   rcr    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 c4 02   rol    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 c0      rol    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 00      rolb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 00 02   roll   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 00      rolw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 04 83   rolw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 00      rol    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 00 02   rol    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 00      rol    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 04 83   rol    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 cc 02   ror    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 c8      ror    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 08      rorb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 08 02   rorl   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 08      rorw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 0c 83   rorw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 08      ror    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 08 02   ror    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 08      ror    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 0c 83   ror    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 fc 02   sar    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 f8      sar    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 38      sarb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 38 02   sarl   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 38      sarw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 3c 83   sarw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 38      sar    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 38 02   sar    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 38      sar    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 3c 83   sar    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 f4 0d 10 81 d8 34 12        sbb    \$0x1234,%ax,%r30w
 \s*[a-f0-9]+:\s*62 7c 6c 10 18 f9      sbb    %r15b,%r17b,%r18b
 \s*[a-f0-9]+:\s*62 54 6c 10 19 38      sbb    %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 1a 04 07   sbb    \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 1b 04 07   sbb    \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 1c 83 11        sbbl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 1c 83 11        sbb    \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02   shl    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02   shl    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0      shl    %cl,%r16b,%r8b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0      shl    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 20      shlb   \$1,\(%rax\),%r31b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 20      shlb   \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 20      shl    \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 20      shl    \$1,\(%rax\),%r31b
 \s*[a-f0-9]+:\s*62 74 84 10 24 20 01   shld   \$0x1,%r12,\(%rax\),%r31
 \s*[a-f0-9]+:\s*62 74 04 10 24 38 02   shld   \$0x2,%r15d,\(%rax\),%r31d
 \s*[a-f0-9]+:\s*62 54 05 10 24 c4 02   shld   \$0x2,%r8w,%r12w,%r31w
 \s*[a-f0-9]+:\s*62 7c bc 18 a5 e0      shld   %cl,%r12,%r16,%r8
 \s*[a-f0-9]+:\s*62 7c 05 10 a5 2c 83   shld   %cl,%r13w,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 74 05 10 a5 08      shld   %cl,%r9w,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02   shll   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02   shll   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 20      shlw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 20      shlw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83   shlw   %cl,\(%r19,%rax,4\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83   shlw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02   shl    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02   shl    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 20      shl    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 20      shl    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83   shl    %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83   shl    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 d4 04 10 c0 ec 02   shr    \$0x2,%r12b,%r31b
 \s*[a-f0-9]+:\s*62 fc 3c 18 d2 e8      shr    %cl,%r16b,%r8b
-\s*[a-f0-9]+:\s*62 f4 04 10 d0 28      shrb   \$1,\(%rax\),%r31b
+\s*[a-f0-9]+:\s*62 f4 04 10 d0 28      shr    \$1,\(%rax\),%r31b
 \s*[a-f0-9]+:\s*62 74 84 10 2c 20 01   shrd   \$0x1,%r12,\(%rax\),%r31
 \s*[a-f0-9]+:\s*62 74 04 10 2c 38 02   shrd   \$0x2,%r15d,\(%rax\),%r31d
 \s*[a-f0-9]+:\s*62 54 05 10 2c c4 02   shrd   \$0x2,%r8w,%r12w,%r31w
 \s*[a-f0-9]+:\s*62 7c bc 18 ad e0      shrd   %cl,%r12,%r16,%r8
 \s*[a-f0-9]+:\s*62 7c 05 10 ad 2c 83   shrd   %cl,%r13w,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 74 05 10 ad 08      shrd   %cl,%r9w,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 f4 04 10 c1 28 02   shrl   \$0x2,\(%rax\),%r31d
-\s*[a-f0-9]+:\s*62 f4 05 10 d1 28      shrw   \$1,\(%rax\),%r31w
-\s*[a-f0-9]+:\s*62 fc 05 10 d3 2c 83   shrw   %cl,\(%r19,%rax,4\),%r31w
+\s*[a-f0-9]+:\s*62 f4 04 10 c1 28 02   shr    \$0x2,\(%rax\),%r31d
+\s*[a-f0-9]+:\s*62 f4 05 10 d1 28      shr    \$1,\(%rax\),%r31w
+\s*[a-f0-9]+:\s*62 fc 05 10 d3 2c 83   shr    %cl,\(%r19,%rax,4\),%r31w
 \s*[a-f0-9]+:\s*62 f4 0d 10 81 e8 34 12        sub    \$0x1234,%ax,%r30w
 \s*[a-f0-9]+:\s*62 7c 6c 10 28 f9      sub    %r15b,%r17b,%r18b
 \s*[a-f0-9]+:\s*62 54 6c 10 29 38      sub    %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 2a 04 07   sub    \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 2b 04 07   sub    \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 2c 83 11        subl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 2c 83 11        sub    \$0x11,\(%r19,%rax,4\),%r20d
 \s*[a-f0-9]+:\s*62 f4 0d 10 81 f0 34 12        xor    \$0x1234,%ax,%r30w
 \s*[a-f0-9]+:\s*62 7c 6c 10 30 f9      xor    %r15b,%r17b,%r18b
 \s*[a-f0-9]+:\s*62 54 6c 10 31 38      xor    %r15d,\(%r8\),%r18d
 \s*[a-f0-9]+:\s*62 c4 3c 18 32 04 07   xor    \(%r15,%rax,1\),%r16b,%r8b
 \s*[a-f0-9]+:\s*62 c4 3d 18 33 04 07   xor    \(%r15,%rax,1\),%r16w,%r8w
-\s*[a-f0-9]+:\s*62 fc 5c 10 83 34 83 11        xorl   \$0x11,\(%r19,%rax,4\),%r20d
+\s*[a-f0-9]+:\s*62 fc 5c 10 83 34 83 11        xor    \$0x11,\(%r19,%rax,4\),%r20d
 #pass

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f2c7959614625c94b8dd053720be51612bf0bf44..6b154ab214af64e2fbe9b337f15cbf60b202cab8 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1769,7 +1769,7 @@ struct dis386 {
 };
 
 /* Upper case letters in the instruction names here are macros.
-   'A' => print 'b' if no register operands or suffix_always is true
+   'A' => print 'b' if no (suitable) register operand or suffix_always is true
    'B' => print 'b' if suffix_always is true
    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
          size prefix
@@ -1788,8 +1788,8 @@ struct dis386 {
    'O' => print 'd' or 'o' (or 'q' in Intel mode)
    'P' => behave as 'T' except with register operand outside of suffix_always
          mode
-   'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
-         is true
+   'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
+         suffix_always is true
    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
    'S' => print 'w', 'l' or 'q' if suffix_always is true
    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
@@ -10416,7 +10416,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
        case 'A':
          if (ins->intel_syntax)
            break;
-         if ((ins->need_modrm && ins->modrm.mod != 3)
+         if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
              || (sizeflag & SUFFIX_ALWAYS))
            *ins->obufp++ = 'b';
          break;
@@ -10715,7 +10715,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
              if (ins->intel_syntax && !alt)
                break;
              USED_REX (REX_W);
-             if ((ins->need_modrm && ins->modrm.mod != 3)
+             if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
                  || (sizeflag & SUFFIX_ALWAYS))
                {
                  if (ins->rex & REX_W)