drm/i915/pps: only touch the vlv_ members on VLV/CHV

While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are
only relevant for VLV/CHV, we still initialize them on all platforms and
check them on BXT/GLK. Wrap all access inside VLV/CHV checks for
consistency.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/158c7b30e56d22aa3f9c9e51e87b9d89687d74d5.1726681620.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9dd86523012fd519616bcea851b3aa9e3a6de442..9f908dbd45ead65c1f28ba52ad58487040f3f338 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6867,8 +6867,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
                return false;
 
        intel_dp->reset_link_params = true;
-       intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
-       intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
 
        /* Preserve the current hw state. */
        intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
@@ -6895,8 +6893,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
        intel_dp_set_default_sink_rates(intel_dp);
        intel_dp_set_default_max_sink_lane_count(intel_dp);
 
-       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+               intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
                intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
+       }
 
        intel_dp_aux_init(intel_dp);
        intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 2d8d911988ab74443d4ebd6b286c4bb8dee9a355..649dc6ad22788d326afa2fb249219845d8fcf7b0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display)
        for_each_intel_dp(display->drm, encoder) {
                struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-               drm_WARN_ON(display->drm,
-                           intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
+               if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+                       drm_WARN_ON(display->drm,
+                                   intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
 
                if (encoder->type != INTEL_OUTPUT_EDP)
                        continue;
 
-               if (DISPLAY_VER(display) >= 9)
-                       intel_dp->pps.bxt_pps_reset = true;
-               else
+               if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                        intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
+               else
+                       intel_dp->pps.bxt_pps_reset = true;
        }
 }