ib_attr->max_pd = dev_attr->max_pd;
        ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
        ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
-       ib_attr->atomic_cap = IB_ATOMIC_HCA;
-       ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
+       if (dev_attr->is_atomic) {
+               ib_attr->atomic_cap = IB_ATOMIC_HCA;
+               ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
+       }
 
        ib_attr->max_ee_rd_atom = 0;
        ib_attr->max_res_rd_atom = 0;
 
                                                     0, 0, 0, 0, 0, 0, 0, 0 } };
 
 /* Device */
+
+static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)
+{
+       int rc;
+       u16 pcie_ctl2;
+
+       rc = pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2,
+                                      &pcie_ctl2);
+       if (rc)
+               return false;
+       return !!(pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);
+}
+
 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
                            struct bnxt_qplib_dev_attr *attr)
 {
                attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
        }
 
+       attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
 bail:
        bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
        return rc;
 
 
 #define BNXT_QPLIB_RESERVED_QP_WRS     128
 
+#define PCI_EXP_DEVCTL2_ATOMIC_REQ      0x0040
+
 struct bnxt_qplib_dev_attr {
        char                            fw_ver[32];
        u16                             max_sgid;
        u32                             max_inline_data;
        u32                             l2_db_size;
        u8                              tqm_alloc_reqs[MAX_TQM_ALLOC_REQ];
+       bool                            is_atomic;
 };
 
 struct bnxt_qplib_pd {