4.19-stable patches

added patches:
	arm64-add-midr-encoding-for-hisilicon-taishan-cpus.patch

diff --git a/queue-4.19/arm64-add-midr-encoding-for-hisilicon-taishan-cpus.patch b/queue-4.19/arm64-add-midr-encoding-for-hisilicon-taishan-cpus.patch
new file mode 100644 (file)
index 0000000..d286861
--- /dev/null
+++ b/queue-4.19/arm64-add-midr-encoding-for-hisilicon-taishan-cpus.patch
@@ -0,0 +1,50 @@
+From efd00c722ca855745fcc35a7e6675b5a782a3fc8 Mon Sep 17 00:00:00 2001
+From: Hanjun Guo <guohanjun@huawei.com>
+Date: Tue, 5 Mar 2019 21:40:57 +0800
+Subject: arm64: Add MIDR encoding for HiSilicon Taishan CPUs
+
+From: Hanjun Guo <hanjun.guo@linaro.org>
+
+commit efd00c722ca855745fcc35a7e6675b5a782a3fc8 upstream.
+
+Adding the MIDR encodings for HiSilicon Taishan v110 CPUs,
+which is used in Kunpeng ARM64 server SoCs. TSV110 is the
+abbreviation of Taishan v110.
+
+Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
+Reviewed-by: John Garry <john.garry@huawei.com>
+Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/include/asm/cputype.h |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/include/asm/cputype.h
++++ b/arch/arm64/include/asm/cputype.h
+@@ -68,6 +68,7 @@
+ #define ARM_CPU_IMP_BRCM              0x42
+ #define ARM_CPU_IMP_QCOM              0x51
+ #define ARM_CPU_IMP_NVIDIA            0x4E
++#define ARM_CPU_IMP_HISI              0x48
+ 
+ #define ARM_CPU_PART_AEM_V8           0xD0F
+ #define ARM_CPU_PART_FOUNDATION               0xD00
+@@ -96,6 +97,8 @@
+ #define NVIDIA_CPU_PART_DENVER                0x003
+ #define NVIDIA_CPU_PART_CARMEL                0x004
+ 
++#define HISI_CPU_PART_TSV110          0xD01
++
+ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+ #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+ #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
+@@ -114,6 +117,7 @@
+ #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
+ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
+ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
++#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
+ 
+ #ifndef __ASSEMBLY__
+ 

diff --git a/queue-4.19/series b/queue-4.19/series
index 865084917ae098fec40a8e8bca206e23c184682f..b741bd32767a11a2f08de0aa1adad244c3a367fc 100644 (file)
--- a/queue-4.19/series
+++ b/queue-4.19/series
@@ -40,6 +40,7 @@ usb-dwc3-gadget-clear-dwc3_ep_transfer_started-on-cm.patch
 alsa-usb-audio-cleanup-dsd-whitelist.patch
 usb-handle-warm-reset-port-requests-on-hub-resume.patch
 rtc-pcf8523-set-xtal-load-capacitance-from-dt.patch
+arm64-add-midr-encoding-for-hisilicon-taishan-cpus.patch
 arm64-kpti-whitelist-hisilicon-taishan-v110-cpus.patch
 mlxsw-spectrum-set-lag-port-collector-only-when-acti.patch
 net-stmmac-fix-napi-poll-in-tx-path-when-in-multi-qu.patch