RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters

When using riscv_v_abi, the return and arguments of the function should
be adequately checked to avoid ICE.

	PR target/118872

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_fntype_abi): Strengthen the logic
	of the check to avoid missing the error report.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr118872.c: New test.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Jin Ma <jinma@linux.alibaba.com>

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6e14126e3a4a82a464d97858861ceba45421c2b9..9bf7713139f67f03642816272105eb3901628f54 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6479,9 +6479,13 @@ riscv_fntype_abi (const_tree fntype)
   /* Implement the vector calling convention.  For more details please
      reference the below link.
      https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389  */
-  if (riscv_return_value_is_vector_type_p (fntype)
-         || riscv_arguments_is_vector_type_p (fntype)
-         || riscv_vector_cc_function_p (fntype))
+  bool validate_v_abi_p = false;
+
+  validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype);
+  validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype);
+  validate_v_abi_p |= riscv_vector_cc_function_p (fntype);
+
+  if (validate_v_abi_p)
     return riscv_v_abi ();
 
   return default_function_abi;

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c
new file mode 100644 (file)
index 0000000..adb54d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c
@@ -0,0 +1,13 @@
+/* Test that we do not have ice when compile */
+/* { dg-do assemble } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2"  { target { rv64 } } } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2"  { target { rv32 } } } */
+
+#include <riscv_vector.h>
+
+vfloat32m2_t foo (vfloat16m1_t a, size_t vl)
+{
+  return __riscv_vfwcvt_f_f_v_f32m2(a, vl);
+}
+
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */