simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.

        * config/arc/simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.
        (UNSPEC_ARC_SIMD_VLD32WL): Likewise.
        (vld32wh_insn, vld32wl_insn): Delete commented-out old
        versions of these patterns.

From-SVN: r203078

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1b9f97ed1ecb6e3312e7483ab478579f4e012bc5..b00b2e3d6b5a54d54e82f7e2049e05593414a3c6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-10-01  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+       * config/arc/simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.
+       (UNSPEC_ARC_SIMD_VLD32WL): Likewise.
+       (vld32wh_insn, vld32wl_insn): Delete commented-out old
+       versions of these patterns.
+
 2013-10-01  Joern Rennecke  <joern.rennecke@embecosm.com>
 
        * config/arc/arc.c (arc_conditional_register_usage):

diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 22daf51fa66f4c61a95064dcd77a4b2478c73a85..15187827478a003f067c17a37a43804fb292d8ec 100644 (file)
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -126,9 +126,6 @@
   (UNSPEC_ARC_SIMD_VRECRUN   1107)
   (UNSPEC_ARC_SIMD_VENDREC   1108)
 
-  (UNSPEC_ARC_SIMD_VLD32WH   1110)
-  (UNSPEC_ARC_SIMD_VLD32WL   1111)
-
   (UNSPEC_ARC_SIMD_VCAST     1200)
   (UNSPEC_ARC_SIMD_VINTI     1201)
    ]
@@ -1195,24 +1192,6 @@
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
-;; Va, [Ib,u8] instructions
-;; (define_insn "vld32wh_insn"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
-;;     (vec_concat:V8HI (unspec:V4HI [(match_operand:SI 1 "immediate_operand" "P")
-;;                                   (vec_select:HI (match_operand:V8HI 2 "vector_register_operand"  "v")
-;;                                                   (parallel [(match_operand:SI 3 "immediate_operand" "L")]))] UNSPEC_ARC_SIMD_VLD32WH)
-;;                      (vec_select:V4HI (match_dup 0)
-;;                                       (parallel[(const_int 0)]))))]
-;; (define_insn "vld32wl_insn"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
-;;     (unspec:V8HI [(match_operand:SI 1 "immediate_operand" "L")
-;;                  (match_operand:SI 2 "immediate_operand" "P")
-;;                  (match_operand:V8HI 3 "vector_register_operand"  "v")
-;;                  (match_dup 0)] UNSPEC_ARC_SIMD_VLD32WL))]
-;;   "TARGET_SIMD_SET"
-;;   "vld32wl %0, [I%1,%2]"
-;;   [(set_attr "length" "4")
-;;   (set_attr "cond" "nocond")])
 (define_insn "vld32wh_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
        (vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")